Scan-out pad frequency optimization with accumulator buffering
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Solution Overview
Problem
The increasing complexity of IC designs and the resulting higher scan volumes lead to longer testing times and increased costs, primarily due to the constraint imposed by slower Scan-OUT pads that limit the scan-shift frequency.
Innovation Solution
The design optimizes scan shift time by unloading all scan chains at a higher frequency and shifting data from slower Scan-OUT pads every other cycle, with accumulated data temporarily stored in an accumulator and then shifted out through faster Scan-OUT pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If scan chains are unloaded at higher frequency, then scan-shift time is reduced, but slow Scan-OUT pads cannot handle the frequency
Solution Approach 1:
The patent segments scan chains into two groups: those connected to fast Scan-OUT pads and those connected to slow Scan-OUT pads. Fast scan chains operate at the higher first frequency while slow scan chains operate at the lower second frequency, allowing the system to achieve high-speed operation for the majority of chains without overloading the slow pads.
Solution Approach 2:
The patent introduces an accumulator as an intermediary component that temporarily stores data from slow scan chains. This accumulator acts as a buffer, allowing slow scan chains to feed data at their limited rate while the system maintains high-speed operation overall, with the accumulator being periodically cleared to fast scan chains for high-speed output.
2Productivity
If more Scan-OUT pads are used, then scan compression is improved, but the presence of slow pads reduces overall scan-shift frequency
Solution Approach 1:
The patent applies different operating frequencies to different groups of Scan-OUT pads based on their individual capabilities. Fast Scan-OUT pads operate at the higher first frequency while slow Scan-OUT pads operate at the lower second frequency, allowing each pad to operate at its optimal speed without constraining the entire system to the slowest pad's frequency.
Solution Approach 2:
The patent dynamically assigns different operating frequencies to different scan chains based on their connected Scan-OUT pad characteristics. The system adapts its operation by clocking fast scan chains at the higher frequency and slow scan chains at the lower frequency, optimizing overall performance rather than using a uniform frequency.
Data Source
AI summary
An integrated circuit improves scan testing efficiency by addressing slow Scan-OUT pins. The integrated circuit shifts data through high-frequency Scan-OUT pins every cycle and through low-frequency Scan-OUT pins every other cycle. Data that cannot be shifted through low-frequency pins is stored in an accumulator and later shifted out through high-frequency pins. Despite changing the scan-out data pattern, the tester used for testing the integrated circuit anticipates the resulting pattern, providing for the testing to not be negatively impacted.