Scan Output Flip-Flop Power Gating
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Solution Overview
Problem
Conventional scan output flip-flops consume unnecessary power due to operating buffers in delay chains during normal mode, leading to increased power consumption without a corresponding area penalty reduction.
Innovation Solution
The design incorporates a selection circuit, control circuit, and scan-out/data-out stage circuits with test enable signals and clock signals to selectively transmit data or test signals, enabling a gating function that keeps scan-out and data-out signals at fixed voltage levels in normal mode, thereby reducing power consumption without significant area increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If buffers in delay chains operate during normal mode, then data transmission is maintained, but power consumption increases unnecessarily
Solution Approach 1:
The patent implements dynamic operation mode switching where buffers in delay chains can be enabled or disabled based on operational mode. During normal mode, buffers are disabled to save power while maintaining data transmission through alternative paths. During test mode, buffers are enabled to support scan chain operations. This dynamic switching resolves the contradiction by adapting buffer operation to actual needs rather than maintaining constant operation.
Solution Approach 2:
The patent applies different operational characteristics to different parts of the circuit based on mode. Specifically, buffers in delay chains associated with scan output flip-flops have their operation selectively controlled - disabled during normal mode for power saving, enabled during test mode for functionality. This local quality approach allows power reduction in specific regions without compromising overall system functionality.
2Use of energy by moving object
If a gating function is applied to scan-out and data-out signals, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The gating function implemented in the patent serves multiple purposes: it acts as a power-saving mechanism by disabling buffers during normal mode, and simultaneously serves as a mode-selection mechanism that routes signals appropriately between normal and test operations. This multi-functionality reduces the need for separate dedicated components, thereby limiting the increase in device complexity while achieving power reduction goals.
Solution Approach 2:
The patent merges the gating function with existing mode control logic and output stage circuits. Rather than adding completely separate gating components, the control signals for buffering are integrated with the existing test enable logic and output enable mechanisms. This merging approach achieves power savings through gating while minimizing additional circuit complexity by reusing existing control infrastructure.
Data Source
AI summary
A scan output flip-flop includes a selection circuit, a control circuit, and a scan-out stage circuit. The selection circuit is controlled by a first test enable signal to transmit a data signal on a first input terminal or a test signal on a second input terminal to an output terminal to serve as an input signal. The control circuit is controlled by a first clock signal and a second clock signal to generate a first control signal and a second control signal according to the input signal. The scan-out stage circuit receives only one of the first control signal and the second control signal, and is controlled by the first test enable signal and a second test enable signal to generate a scan-out signal.