Scan Path Interface Circuit Reducing Memory Requirements
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Solution Overview
Problem
Conventional device scan testing methods require large and high-speed stimulus and expected data memories, leading to increased costs due to the need for extensive memory storage and rapid data shifting in parallel scan path approaches.
Innovation Solution
The method involves using a formatter circuit to reuse response data patterns from a circuit under test to provide both stimulus and expected data patterns, reducing the need for large memory storage and high-speed data shifting by converting response bit streams into stimulus and expected data streams within the circuit itself.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel scan paths are used to input stimulus patterns and capture response patterns, then testing capability is improved, but memory size and operational speed requirements increase
Solution Approach 1:
The circuit under test generates its own expected response patterns by processing compressed stimulus patterns through internal logic, eliminating the need for external expected data memory. The circuit essentially tests itself by comparing actual responses against internally generated expected responses.
Solution Approach 2:
The patent extracts the expected data generation function from the external tester system and relocates it within the circuit under test. This removes the need for large expected data memory in the tester while maintaining full testing capability.
2Productivity
If parallel scan paths are used to input stimulus patterns and capture response patterns, then testing capability is improved, but memory operational speed requirements increase
Solution Approach 1:
The circuit under test generates its own expected response patterns by processing compressed stimulus patterns through internal logic, eliminating the need for external expected data memory. The circuit essentially tests itself by comparing actual responses against internally generated expected responses.
Solution Approach 2:
The patent extracts the expected data generation function from the external tester system and relocates it within the circuit under test. This removes the need for large expected data memory in the tester while maintaining full testing capability.
3Reliability
If large high-speed memories are used for stimulus and expected data storage, then testing completeness is improved, but device cost increases
Solution Approach 1:
The circuit under test generates its own expected response patterns by processing compressed stimulus patterns through internal logic, eliminating the need for external expected data memory. The circuit essentially tests itself by comparing actual responses against internally generated expected responses.
Solution Approach 2:
The patent extracts the expected data generation function from the external tester system and relocates it within the circuit under test. This removes the need for large expected data memory in the tester while maintaining full testing capability.
Data Source
AI summary
The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.