Scan Pattern Alignment for Broadcast Scan Enable Across IC Blocks
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Solution Overview
Problem
In integrated circuit (IC) designs, particularly in system-on-chip (SoC) designs, different cores often have varying scan pattern shift lengths, leading to issues in aligning scan chains for simultaneous testing, which can result in inefficient test time and the need for regenerating scan patterns due to engineering changes, especially when cores with existing scan architectures are modified.
Innovation Solution
The solution involves adjusting scan pattern shift lengths across multiple circuit blocks in an IC design by determining a common minimal length and modifying existing scan patterns through pre- or post-padding to ensure all cores align with this length, allowing a unified scan enable signal to be broadcasted, thus optimizing test time and avoiding the need to regenerate patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scan patterns are generated for different circuit blocks with varying scan chain lengths, then each circuit block can be tested independently, but the scan enable signal cannot be broadcast simultaneously to multiple circuit blocks, increasing test time
Solution Approach 1:
The patent modifies scan pattern parameters (length and content) to accommodate different scan chain lengths in various circuit blocks. By adjusting the scan pattern length to match the longest scan chain and modifying pattern content through pre-padding or post-padding techniques, the system enables simultaneous broadcasting of scan enable signals to multiple circuit blocks, thereby reducing overall test time while maintaining independent testability of each block
Solution Approach 2:
The patent segments the scan pattern modification process into distinct approaches: pre-padding (adding dummy cycles before the actual test pattern) and post-padding (adding dummy cycles after the actual test pattern). This segmentation allows flexible adjustment of scan pattern lengths for different circuit blocks without affecting the core test functionality, enabling synchronized scan enable signal broadcasting across multiple blocks with varying scan chain lengths
2Ease of operation
If scan patterns are modified to align lengths across circuit blocks, then a unified scan enable signal can be broadcast to multiple blocks, but the scan pattern content must be changed through pre-padding or post-padding
Solution Approach 1:
The patent applies pre-padding by adding dummy scan cycles before the actual test pattern is applied to circuit blocks with shorter scan chains. This preliminary action aligns the scan pattern length with the longest scan chain in the system, enabling unified scan enable signal broadcasting without requiring modifications to the core test pattern logic or circuit block designs
Solution Approach 2:
Instead of modifying the scan patterns of circuit blocks with longer scan chains to match shorter ones (which would require complex truncation and regeneration), the patent inverts the approach by extending shorter scan patterns to match the longest scan chain length. This inversion simplifies the modification process by only adding content rather than removing or regenerating patterns, reducing overall system complexity
Data Source
AI summary
A first scan pattern may be received to test a first circuit block in an integrated circuit (IC) design and a second scan pattern may be received to test a second circuit block in the IC design. A first length of the first scan pattern may be different from a second length of the second scan pattern. The first scan pattern, the second scan pattern, or both the first scan pattern and the second scan pattern may be modified to make lengths of the first scan pattern and the second scan pattern equal.