Scan Pattern Reformatting for Hold-Pipeline DFT Timing
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Solution Overview
Problem
The presence of hold type pipelines in scan-based integrated circuit designs increases scan test time proportionally with the number of pipeline stages, leading to inefficiencies in test-cost and coverage, especially in large and complex designs.
Innovation Solution
Reformatting scan patterns into pipeline-independent patterns (PIP) that utilize the state-holding nature of pipeline stages during capture, splitting each pattern into parts that are loaded across different cycles to maintain the same shift length, thereby reducing the impact of pipeline stages on test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If hold type pipelines are added to meet timing requirements in scan-based designs, then timing closure is achieved, but scan test time increases proportionally with the number of pipeline stages
Solution Approach 1:
The patent segments the scan pattern into multiple sections, with each section corresponding to a specific pipeline stage. By dividing the monolithic scan pattern into smaller manageable sections, the test can be performed in parallel across multiple pipeline stages, eliminating the proportional increase in test time while maintaining timing closure requirements
Solution Approach 2:
The patent introduces a new dimension of parallelism by operating on multiple pipeline stages simultaneously rather than sequentially. This transforms the test approach from a single-dimensional sequential process to a multi-dimensional parallel process, where scan patterns are applied across different pipeline stages in parallel, thus decoupling test time from the number of pipeline stages
2Reliability
If scan chain length increases to cover more scan flops in large designs, then fault coverage improves, but test time increases directly with scan chain length
Solution Approach 1:
The patent divides the long scan chain into multiple segments corresponding to different pipeline stages, allowing fault coverage to be achieved across the entire scan chain while testing each segment in parallel. This segmentation enables comprehensive fault coverage without the test time increasing linearly with the total scan chain length
Solution Approach 2:
The patent performs preliminary actions by pre-processing and reformatting scan patterns into pipeline-independent patterns that are optimized for parallel application across multiple pipeline stages. This preliminary preparation enables subsequent parallel testing, reducing overall test time while maintaining comprehensive fault coverage
Data Source
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AI summary
A method includes identifying state holding pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design, splitting each pattern of a plurality of patterns into a first part and a second part, reformatting the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns. The length of the first part is a function of a number of the identified pipeline stages.