Scan Pipelining Optimization for Hierarchical Test Design
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Solution Overview
Problem
In electronic design automation, the existing methods for design for testing (DFT) in semiconductor integrated circuits face challenges in optimizing scan pipelining, leading to area overhead and timing issues due to the manual insertion of pipeline flip-flops and suboptimal clocking, especially in hierarchical test designs where blocks are physically distant.
Innovation Solution
A processor-based method generates optimized scan chains with variable pipeline stages and correct clocking, inserting pipeline flip-flops and lockup elements to meet timing requirements and reduce area overhead by customizing pipeline depth based on physical distances between blocks, eliminating the need for additional lockup elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pipeline flip-flops are inserted to meet timing requirements in hierarchical test design, then timing compliance is improved, but area overhead increases due to additional lockup elements
Solution Approach 1:
The patent applies local quality by determining the required pipeline depth individually for each scan chain based on its specific timing requirements and physical distance, rather than uniformly across all scan chains. This allows optimal insertion of pipeline flip-flops only where needed, reducing overall area overhead while meeting timing compliance.
Solution Approach 2:
The patent changes the parameter of pipeline depth (number of pipeline stages) dynamically for different scan chains based on their specific timing requirements. By calculating the required pipeline depth for each scan chain individually, the system optimizes the balance between timing compliance and area overhead.
2Productivity
If scan chains are optimized for high scan shift frequency, then productivity is improved, but timing requirements become harder to meet due to longer propagation delays
Solution Approach 1:
The patent introduces dynamic pipeline staging by allowing the number of pipeline stages to vary for different scan chains based on their specific timing and distance requirements. This dynamic approach enables the system to maintain high scan shift frequencies while meeting timing constraints by adding pipeline stages only where necessary.
Solution Approach 2:
The patent segments the scan chains into different groups based on their timing requirements and physical distances, applying different pipeline depths to each segment. This segmentation allows the system to optimize scan shift frequency for each segment independently, maintaining high overall productivity while ensuring timing compliance.
3Reliability
If manual insertion of pipeline flip-flops is performed, then timing requirements can be met, but device complexity increases due to suboptimal clocking and additional lockup elements
Solution Approach 1:
The patent implements self-service by providing an automated methodology that calculates the required pipeline depth for each scan chain and determines the appropriate clocking scheme without manual intervention. This automation reduces device complexity by eliminating suboptimal manual insertions and unnecessary lockup elements.
Solution Approach 2:
The patent uses feedback from timing analysis and physical distance measurements to automatically determine the optimal pipeline depth for each scan chain. This feedback-driven approach reduces device complexity by precisely inserting only the necessary number of pipeline flip-flops and lockup elements, avoiding over-engineering.
Data Source
AI summary
A system for optimizing scan pipelining may include a processor and a memory. The processor may generate and insert, based on prior analysis of the physical layout of the circuit, an optimized number of pipeline stages between a first block and a second block in a hardware test design, a first scan chain including at least one pipeline stage of a head pipeline stage or a tail pipeline stage. The processor may insert a plurality of flip-flops into the first scan chain. The processor may determine at least one clock to be used for the at least one pipeline stage, using the plurality of flip-flops so as to eliminate the need of a lockup element between the at least one pipeline stage and the plurality of flip-flops. The processor may generate, based on the at least one clock, a second scan chain that connects the at least one pipeline stage and the plurality of flip-flops.