Scan and Non-Scan Register Layout for Full IC Test Coverage
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Solution Overview
Problem
Existing integrated circuit designs face challenges in achieving full scan testability with reduced circuit area, power consumption, and leakage power, while partial scan-enabled designs suffer from unknown states leading to increased test time and reduced test coverage.
Innovation Solution
Implementing a scan register connected to non-scan registers via a multiplexer, allowing scan insertion signals to be fed back to non-scan registers during scan testing, thereby sharing their state and enhancing test coverage without increasing circuit area or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all registers are scan-enabled to achieve full test coverage, then test coverage is improved, but circuit area and power consumption increase
Solution Approach 1:
The patent segments the register set into two groups: scan-enabled registers and non-scan registers. This segmentation allows only the necessary portion of registers to be scan-enabled, reducing the overall circuit area and power consumption while maintaining adequate test coverage through the selective scanning of critical registers.
Solution Approach 2:
Different quality levels of scan capability are applied to different parts of the circuit. Critical registers that require full test coverage are scan-enabled, while less critical registers remain non-scan. This local differentiation optimizes the balance between test coverage and resource consumption.
2Reliability
If all registers are scan-enabled to achieve full test coverage, then test coverage is improved, but power consumption increases
Solution Approach 1:
The patent segments the register set into two groups: scan-enabled registers and non-scan registers. This segmentation allows only the necessary portion of registers to be scan-enabled, reducing the overall circuit area and power consumption while maintaining adequate test coverage through the selective scanning of critical registers.
Solution Approach 2:
Different quality levels of scan capability are applied to different parts of the circuit. Critical registers that require full test coverage are scan-enabled, while less critical registers remain non-scan. This local differentiation optimizes the balance between test coverage and resource consumption.
3Area of stationary object
If partial scan-enablement is used to reduce circuit area, then circuit area is reduced, but test coverage decreases
Solution Approach 1:
The patent implements feedback mechanisms that allow non-scan registers to receive scan insertion signals from scan-enabled registers. This feedback approach enables the non-scan registers to be indirectly tested through the scan chain, thereby improving test coverage without requiring all registers to be scan-enabled, thus maintaining reduced circuit area.
4Area of stationary object
If partial scan-enablement is used to reduce circuit area, then circuit area is reduced, but test time increases
Solution Approach 1:
The patent implements feedback mechanisms that allow non-scan registers to receive scan insertion signals from scan-enabled registers. This feedback approach enables the non-scan registers to be indirectly tested through the scan chain, thereby improving test coverage without requiring all registers to be scan-enabled, thus maintaining reduced circuit area.
Data Source
AI summary
Briefly, example apparatuses, articles of manufacture, and/or techniques are disclosed that may be implemented, in whole or in part, to implement, facilitate and/or support integrated circuit design-for-testing, such as, a scan register coupled to one or more non-scan registers via a multiplexer having first and second signal inputs.