Scan Reset Control Circuit for IR Drop Mitigation in IC Testing
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Solution Overview
Problem
Conventional testing methods for integrated circuits cause undesirable IR drop due to simultaneous toggling of large numbers of flip-flops, leading to voltage drops that can destabilize components like phase-locked loop circuits, resulting in pattern failures and instabilities.
Innovation Solution
A scan reset control circuit that receives a reset signal and generates circuit block-specific reset signals using writable non-scan test data registers and reset enable circuits, allowing selective activation and deactivation of circuit blocks to mitigate IR drop during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simultaneous reset signals are applied to all circuit blocks, then comprehensive fault coverage is achieved, but IR drop increases causing voltage instability
Solution Approach 1:
The patent segments the reset signal distribution by introducing a scan reset control circuit that divides circuit blocks into multiple groups. Each group receives reset signals independently through separate scan reset outputs, preventing simultaneous reset of all blocks and thereby reducing overall IR drop while maintaining comprehensive fault coverage through systematic testing of each segment.
Solution Approach 2:
The patent implements dynamic control of reset signal timing through the scan reset control circuit. The circuit dynamically selects which circuit blocks receive reset signals at any given time based on test requirements, allowing flexible timing control that prevents simultaneous reset of all blocks while ensuring all blocks are tested for faults.
2Reliability
If all flip-flops are toggled simultaneously for testing, then complete test coverage is achieved, but voltage drops destabilize components like phase-locked loop circuits
Solution Approach 1:
The patent segments the flip-flop population into multiple groups distributed across different circuit blocks. The scan reset control circuit enables simultaneous toggling of scan flip-flops within each segment while preventing simultaneous toggling across all segments, thereby reducing peak current demand and voltage drops that would destabilize sensitive components like phase-locked loop circuits.
Solution Approach 2:
The patent employs preliminary action by loading test patterns into scan registers before actual testing. The scan reset control circuit prepares and sequences the activation of reset signals to specific circuit blocks before test patterns are applied, ensuring that voltage-sensitive components are protected from simultaneous toggling while maintaining complete test coverage.
3Device complexity
If a single reset signal is used for all circuit blocks, then device complexity is minimized, but IR drop causes pattern failures and instabilities
Solution Approach 1:
The patent implements universality through the scan reset control circuit that serves multiple functions: it distributes reset signals to different circuit blocks, controls test pattern application, and manages timing sequences. This multi-functional approach increases device complexity only slightly while preventing IR drop-induced pattern failures and instabilities through intelligent signal routing and timing control.
Data Source
AI summary
A scan reset control circuit includes a single scan reset input configured to receive a reset signal, a plurality of scan reset outputs configured to be coupled to a plurality of circuit blocks in a one-to-one ratio, a plurality of writable non-scan test data registers including register outputs configured to assert or deassert the reset signal, and a plurality of reset enable circuits coupled to the plurality of scan reset outputs in a one-to-one ratio. Each of the scan reset outputs is configured to simultaneously reset a set of scan flip-flops of the corresponding circuit block. Each of the plurality of reset enable circuits includes an input coupled to the single scan reset input, a selector input coupled to the register outputs, and an output coupled to the corresponding scan reset output.