Scan Reset Circuit Segmentation to Mitigate Test IR Drops
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Solution Overview
Problem
Conventional integrated circuit testing methods cause undesirable IR drops due to simultaneous toggling of large numbers of flip-flops, leading to voltage instability and potential failure in components like phase-locked loop circuits.
Innovation Solution
A scan reset control circuit that generates circuit block-specific reset signals using writable non-scan test data registers and reset enable circuits, allowing selective activation and deactivation of circuit blocks to mitigate IR drops during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reset signal is applied to all flip-flops simultaneously during testing, then complete reset network coverage is achieved, but IR drops and voltage instability occur
Solution Approach 1:
The patent divides the circuit blocks into multiple groups, where each group is associated with a separate test data register. Instead of resetting all flip-flops simultaneously across the entire circuit, the reset signal is applied selectively to specific groups of circuit blocks. This segmentation allows complete reset network coverage to be achieved through multiple staged reset operations rather than a single simultaneous reset, thereby avoiding IR drops and voltage instability.
2Object-affected harmful factors
If circuit blocks are reset in groups, then IR drops are reduced, but test complexity increases
Solution Approach 1:
The patent employs a universal test data register structure where each register can control the reset signal distribution to its associated group of circuit blocks. The same register architecture and control mechanism is reused across all groups, providing a unified and systematic approach to grouped resetting. This multi-functional design allows the test controller to manage multiple circuit block groups using consistent control logic, thereby reducing overall test complexity despite the segmented reset approach.
3Productivity
If all circuit blocks are tested simultaneously, then testing efficiency is high, but voltage stability deteriorates
Solution Approach 1:
The patent implements periodic reset actions by dividing the reset operation into multiple sequential phases, with each phase targeting a specific group of circuit blocks. Instead of a single simultaneous reset event that causes voltage instability, the reset signal is applied periodically to different groups in succession. This periodic approach maintains voltage stability while still achieving complete reset network coverage through the cumulative effect of multiple reset phases.
Data Source
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AI summary
A scan reset control circuit includes a single scan reset input configured to receive a reset signal, a plurality of scan reset outputs configured to be coupled to a plurality of circuit blocks in a one-to-one ratio, a plurality of writable non-scan test data registers including register outputs configured to assert or deassert the reset signal, and a plurality of reset enable circuits coupled to the plurality of scan reset outputs in a one-to-one ratio. Each of the scan reset outputs is configured to simultaneously reset a set of scan flip-flops of the corresponding circuit block. Each of the plurality of reset enable circuits includes an input coupled to the single scan reset input, a selector input coupled to the register outputs, and an output coupled to the corresponding scan reset output.