Scan Segment Bypass Circuitry for IC Test Power Reduction
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Solution Overview
Problem
Integrated circuits experience high power consumption and extended test times during scan testing due to increased switching activity, leading to potential signal integrity issues and reduced yield.
Innovation Solution
The implementation of scan segment bypass circuitry, which separates scan chains into segments and uses multiplexers and a finite state machine to selectively bypass these segments during testing, reducing power consumption and test time without degrading performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan chains are used for testing integrated circuits, then fault detection capability is improved, but power consumption increases significantly
Solution Approach 1:
The scan chain is divided into multiple segments with segment identifiers assigned to each scan cell. The bypass control logic selectively bypasses segments based on their identifiers, allowing only necessary segments to be tested while skipping others, thereby reducing power consumption during scan testing.
Solution Approach 2:
The scan chain configuration is made dynamic through the bypass control logic that can selectively enable or disable segment testing based on segment identifiers. This dynamic control allows the system to adaptively reduce power consumption by bypassing unnecessary segments while maintaining fault detection capability for critical segments.
2Reliability
If scan chains are used for testing integrated circuits, then fault detection capability is improved, but test time increases
Solution Approach 1:
The scan chain is segmented into multiple sections with unique identifiers. The bypass control logic uses these identifiers to selectively bypass segments that do not require testing, allowing the test process to focus only on necessary segments and thereby reducing overall test time while maintaining fault detection capability.
Solution Approach 2:
The bypass control logic enables the test system to skip over segments that are not required for testing by comparing segment identifiers against a selection criteria. This skipping mechanism allows the test pattern to rapidly pass through non-critical segments, significantly reducing test time without compromising the detection of faults in critical segments.
3Reliability
If high switching activity occurs during scan testing, then test coverage is improved, but signal integrity deteriorates due to voltage variations and noise
Solution Approach 1:
The scan chain is divided into segments with unique identifiers. The bypass control logic selectively activates only the segments necessary for achieving adequate test coverage, thereby reducing the overall switching activity in the scan chain. This reduction in switching activity minimizes voltage variations and noise, improving signal integrity while maintaining sufficient test coverage.
Solution Approach 2:
Instead of activating the entire scan chain for testing, the bypass control logic enables only the necessary segments based on identifier matching. This partial action approach achieves adequate test coverage for critical segments while avoiding the excessive switching activity that would otherwise degrade signal integrity through voltage variations and noise.
Data Source
AI summary
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, wherein the scan chain is separated into a plurality of scan segments with each such segment comprising a distinct subset of two or more of the plurality of scan cells. The scan test circuitry further comprises scan segment bypass circuitry configured to selectively bypass one or more of the scan segments in a scan shift mode of operation. The scan segment bypass circuitry may comprise a plurality of multiplexers and a scan segment bypass controller. The multiplexers are arranged within the scan chain and configured to allow respective ones of the scan segments to be bypassed responsive to respective bypass control signals generated by the scan segment bypass controller.


