Scan Storage Circuits for High-Speed Data Retrieval
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Solution Overview
Problem
Current gate-level timing simulations for integrated circuit verification are excessively time-consuming, especially for large designs, and traditional hardware emulation methods lack efficient data retrieval and filtering capabilities, leading to delays and unnecessary data extraction.
Innovation Solution
The proposed integrated circuit design incorporates a clock distribution network, enable circuits, and multiplexers to facilitate high-speed data retrieval through scan chains, allowing for non-destructive read-back operations and filtering of data, thereby reducing execution time and data volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-level timing simulation is used for circuit verification, then verification can be performed with software models, but execution time becomes excessively long for large circuit designs
Solution Approach 1:
The patent replaces software-based gate-level timing simulation with hardware-based emulation using a configurable integrated circuit. The hardware emulator executes the circuit design and test bench in parallel, providing accurate verification results while reducing execution time from hours/days to minutes/seconds through physical hardware acceleration rather than software processing.
Solution Approach 2:
The patent creates a hardware copy of the circuit design on a configurable integrated circuit platform. This hardware replica allows parallel execution of the design and test bench, enabling fast verification without modifying the original design. The scan storage circuits capture and store state values from this hardware copy for analysis.
2Productivity
If traditional hardware emulation is used for fast verification, then execution time is reduced, but data retrieval and filtering capabilities are inefficient leading to delays
Solution Approach 1:
The patent introduces scan storage circuits as intermediary elements between the user storage circuits and the external analysis tools. These scan storage circuits capture state values during emulation and provide them through a controlled scan interface, enabling efficient selective data retrieval and filtering without disrupting the high-speed parallel emulation process.
Solution Approach 2:
The patent performs preliminary data capture and storage in scan storage circuits during the emulation process. By pre-capturing state values in dedicated scan storage elements before analysis is needed, the system eliminates delays associated with real-time data extraction and filtering, allowing fast verification while maintaining efficient data access.
3Loss of information
If all data is extracted from user storage circuits for verification, then complete analysis is achieved, but data extraction overhead and unnecessary data transfer increase
Solution Approach 1:
The patent extracts only the necessary state data from user storage circuits through the scan storage circuits. Rather than extracting all data from all storage elements, the scan chain selectively captures and transfers only the relevant state values needed for verification, reducing data extraction overhead and unnecessary data transfer while maintaining complete analysis capability.
Solution Approach 2:
The patent implements partial data extraction by capturing state values from selected user storage circuits through the scan storage circuits. This partial action approach extracts only the essential data needed for verification rather than all possible data, reducing extraction overhead and energy consumption while sufficient for complete verification analysis.
Data Source
AI summary
An integrated circuit may include user storage circuits and scan storage circuits. The scan storage circuits may store data from the user storage circuits and provide the data to a user interface during a read-back operation. The user storage circuits may store data from the scan storage circuits, which the scan storage circuits may have received from the user interface during a write-back operation. The scan storage circuits may be arranged in a scan chain and controlled by a local control circuit. The integrated circuit may include multiple local control circuits that each control a sector of the integrated circuit. The local control circuits may communicate with a global control circuit over a communication network, and the global control circuit may communicate with the user interface.