Scan Test Circuit Asynchronous Control Flip-Flop
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Solution Overview
Problem
Conventional scan test circuits for semiconductor integrated circuits require complex data sets and longer operation frequencies for delay fault detection, limiting their ability to test at desired speeds and complicating the internal circuit structure.
Innovation Solution
A scan test circuit utilizing a control flip-flop that operates in asynchronous mode with the input clock, allowing for a simplified circuit structure and reduced test pattern length for delay fault detection by using a set flip-flop to control the scan enable signal switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional scan test circuits are used for delay fault detection, then fault detection capability is provided, but the circuit structure becomes complex and test pattern length increases
Solution Approach 1:
The patent extracts and removes the unnecessary multiple combination circuits from the conventional scan test circuit structure. By using a control flip-flop to generate scan enable signals directly from the input clock, the circuit eliminates the need for separate combination circuits that would otherwise be required to generate test patterns, thereby simplifying the overall circuit structure while maintaining fault detection capability
Solution Approach 2:
The control flip-flop is designed to perform multiple functions: it generates scan enable signals for both shift operation mode and capture operation mode, and can operate in asynchronous mode with the input clock. This multi-functionality replaces what would traditionally require multiple separate circuits, reducing complexity while maintaining comprehensive test capability
2Speed
If conventional scan test circuits operate at desired speeds, then operation speed is improved, but test pattern length increases and circuit structure becomes more complex
Solution Approach 1:
The control flip-flop operates dynamically in asynchronous mode with the input clock, allowing the scan test circuit to operate at desired speeds without requiring complex synchronous control circuits. The asynchronous operation enables flexible timing control that maintains high speed while simplifying the circuit structure
Solution Approach 2:
The patent changes the operational parameters of the control flip-flop to operate asynchronously with the input clock, rather than synchronously. This parameter change enables the circuit to operate at desired speeds while avoiding the need for complex clock synchronization and control circuits that would otherwise be required
3Reliability
If multiple combination circuits are used for delay fault detection, then detection accuracy is improved, but circuit structure becomes more complex
Solution Approach 1:
The patent removes the multiple combination circuits from the conventional design and replaces them with a single control flip-flop that generates scan enable signals directly from the input clock. This extraction maintains detection accuracy by preserving the essential test pattern generation functionality while eliminating unnecessary circuit components
Solution Approach 2:
The control flip-flop is designed to generate its own scan enable signals directly from the input clock without requiring external combination circuits. This self-service capability maintains detection accuracy while significantly simplifying the circuit structure, as the control flip-flop autonomously performs the function that would otherwise require multiple separate circuits
Data Source
AI summary
A scan test circuit in the present invention includes a control FF for inputting a control signal, and a scan path chain configured of scan storage elements to operate in a shift operation mode when an output of the control FF is a first status value, and in a normal operation mode when the output is a second status value. When the control signal is switched from the first status value to the second status value, the control FF outputs the second status value to multiple scan storage elements synchronously with a first clock pulse, after the switching, of a clock provided to multiple scan storage elements. When the scan control signal is switched from the second status value to the first status value, the control FF outputs the first status value to multiple scan storage elements at a timing of the control signal switching.