Scan Test Circuit Sampling for X-Density Reduction
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Solution Overview
Problem
The increasing complexity of integrated circuits (ICs) leads to larger scan chains, which require more shift cycles and memory for testing, and high X-density during scan testing, limiting the effectiveness of compression algorithms and increasing test costs.
Innovation Solution
A scan test circuit with multiple clock signals and sampling mechanisms that offset and overlap scan chain output signals, allowing for increased sampling rates and reduced X-density by distributing unknown data across multiple clock cycles, thereby reducing the number of required scan chains and memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan chain size is increased to accommodate larger ICs, then coverage of testing is improved, but number of shift cycles and memory requirements increase
Solution Approach 1:
The patent divides the scan chains into multiple groups that can be operated independently. Each group has its own clock signal and sampling mechanism, allowing parallel testing of different scan chain segments. This segmentation reduces the total number of shift cycles required by enabling simultaneous testing of multiple chains rather than sequential testing of a single long chain.
Solution Approach 2:
The patent employs periodic sampling at different times during clock cycles. Multiple scan chain outputs are sampled at different periods within a clock cycle, and these samples are combined to produce compressed test data. This periodic sampling approach allows efficient capture of data from multiple scan chains without requiring additional time for each chain.
2Reliability
If scan chain size is increased to accommodate larger ICs, then coverage of testing is improved, but memory requirements increase
Solution Approach 1:
By segmenting scan chains into multiple groups with independent clocking and sampling, the patent reduces the amount of data that needs to be stored in memory. Instead of capturing and storing complete test vectors for all scan chains simultaneously, the system captures and stores only the compressed results from each segment, significantly reducing memory requirements while maintaining comprehensive testing coverage.
Solution Approach 2:
The patent introduces compression logic as an intermediary between the scan chains and the memory/storage system. This compression logic processes the test data from multiple scan chains and produces compressed test vectors that require much less memory to store. The compression mechanism acts as a mediator that reduces data volume while preserving essential test information.
3Quantity of substance
If compression algorithms are used to reduce data volume, then memory requirements are reduced, but high X-density limits effectiveness
Solution Approach 1:
The patent segments the scanning and sampling process into distinct phases for different scan chain groups. By separating the operations and using different clock signals, the system reduces the density of unknown values (Xs) in the compressed data. This segmentation allows compression algorithms to work more effectively on data with lower X-density, improving compression effectiveness while reducing memory requirements.
Data Source
AI summary
A scan test circuit includes tester inputs that receive scan test data. Scan chains are coupled to the tester inputs. The tester outputs are coupled to the scan chains and provide output test data based on the scan test data. A first clock generates a first clock signal. A sampling circuit samples each of the tester outputs at least twice per clock cycle of the first clock signal.