Scan Test Input Bus Multiplexing via Clock Edge Separation
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Solution Overview
Problem
Current scan test architectures require additional inputs for expected and mask data, increasing the number of interconnects between devices and testers, which raises costs due to the need for separate input buses for each device during parallel testing.
Innovation Solution
The proposed solution utilizes the falling edge of the scan clock to input expected data, mask data, and test control signals into devices using the same test leads that input test signals on the rising edge, eliminating the need for separate inputs and reducing interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate inputs for expected data and mask data are provided to devices, then scan test functionality is achieved, but the number of interconnects between tester and devices increases
Solution Approach 1:
The patent combines the input functions for test data, expected data, and mask data into a single shared input bus. Multiple data streams are multiplexed onto the same physical interconnect, reducing the total number of connections required between the tester and devices under test while maintaining all necessary scan test functionalities.
Solution Approach 2:
The input bus is designed to serve multiple purposes by accepting different types of data (test stimuli, expected results, mask patterns) through the same interface. The system enables a single interconnect structure to fulfill multiple test data transmission roles, eliminating the need for separate dedicated input lines for each data type.
2Reliability
If separate input buses are provided for each device during parallel testing, then each device receives dedicated test signals, but the cost of the tester increases
Solution Approach 1:
The patent merges multiple device input requirements into shared tester output buffers that drive common interconnects. Multiple devices share the same physical bus infrastructure for receiving test data, expected data, and mask data, significantly reducing the tester's output buffer requirements and overall cost while maintaining parallel testing capability.
Solution Approach 2:
The system uses scan chain architectures where test data can be copied and distributed to multiple devices through shared interconnects. The same test stimulus can be replicated across multiple devices via the common input bus, eliminating the need for completely separate signal paths for each device.
3Adaptability or versatility
If additional inputs are provided for expected and mask data, then complete test control is achieved, but the number of device inputs increases
Solution Approach 1:
The patent implements a universal input interface that accepts multiple types of test control data (stimuli, expected results, mask patterns) through the same physical input pins. The device's scan chain architecture enables a single input structure to handle diverse test data types by sequentially loading different data types into the same register structures.
Solution Approach 2:
The system uses periodic clocking cycles to differentiate between loading test data, expected data, and mask data into the scan chains. By utilizing different phases of the test cycle and control signal sequences, the device can distinguish and properly process multiple data types through the same physical input interface without requiring separate dedicated pins for each data type.
Data Source
AI summary
The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.


