Scan Test Clock Patterns for Multi-Cycle Path Fault Detection
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Solution Overview
Problem
Existing testing methods for hardware integrated circuits, particularly for multi-cycle paths, are inadequate as they assume all paths have single-cycle closure, leading to incomplete fault detection and verification.
Innovation Solution
A technique involving enabling and disabling multi-cycle paths using clock patterns and masks to simulate single-cycle closure, allowing accurate fault detection and verification by aligning the clock rate with the cycle closure of multi-cycle paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If existing testing methods assume all paths have single-cycle closure, then testing simplicity is maintained, but fault detection completeness deteriorates
Solution Approach 1:
The testing method dynamically adapts to different path types by detecting whether a path is single-cycle or multi-cycle and applying appropriate testing strategies. The system transitions from a static single-cycle assumption to a dynamic approach that adjusts testing parameters based on actual path characteristics, enabling comprehensive fault detection across diverse path types without increasing overall method complexity
Solution Approach 2:
The invention changes the testing parameters (such as test pattern generation, clock cycle timing, and path enabling/disabling) based on the detected path type. For multi-cycle paths, the system modifies parameters like test duration, clock frequency, and enable signal timing to match the longer propagation delays, thereby achieving complete fault detection while maintaining testing simplicity through automated parameter adaptation
2Measurement precision
If multi-cycle paths are properly tested with appropriate clock patterns, then fault detection accuracy is improved, but testing time increases
Solution Approach 1:
The testing process is segmented into distinct phases: single-cycle path testing, multi-cycle path detection, and targeted multi-cycle path testing. By dividing the overall testing workflow and applying specialized techniques only where needed, the system achieves high fault detection accuracy for multi-cycle paths without unnecessarily extending the testing time for the entire circuit
Solution Approach 2:
The system applies partial action by focusing detailed multi-cycle testing only on paths that are detected to require it, rather than applying extended testing protocols to all paths. This selective approach ensures high measurement precision for critical multi-cycle paths while minimizing the overall time loss by avoiding excessive testing on paths that don't require it
Data Source
AI summary
A disclosed technique includes based on a clock pattern, determining an enable configuration for setting enable signals for one or more multi-cycle paths of a hardware logic network, setting the enable configuration for the one or more multi-cycle paths, and executing testing operations for the hardware logic network with the one or more multi-cycle paths enabled according to the enable configuration.