Scan Test Multiplexing for ATE Channel Efficiency

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Solution Overview

Problem

State-of-the-art automated test equipment (ATE) systems face challenges in efficiently testing integrated circuit (IC) devices with a large number of input/output (IO) pins due to limited test channels, leading to increased capital costs and decreased test throughput, as conventional multiplexing methods double scan test time and reduce test coverage.

Innovation Solution

A multiplexer is used to couple multiple IC device IO pins to multiple test sites, allowing parallel scan in/out operations during a single phase and selective data capture/drive in launch/capture phases, thereby reducing the need for repeated test patterns and leveraging shared test channels across sites.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conventional multiplexing methods are used to reduce the number of test channels, then capital cost is reduced, but scan test time is doubled and test throughput decreases

Engineering Contradiction:
Improvenumber of test channelsVSAvoidtest throughput
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments the scan test process into two distinct phases: a shared scan-in phase where multiple DUTs are loaded in parallel, and individual scan-out phases where each DUT is tested separately. This segmentation allows the scan data to be shifted into multiple devices simultaneously while maintaining the ability to test each device individually, thereby reducing the need for multiplexing during the time-critical scan-out operation and preserving test throughput.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a temporal dimension to the multiplexing strategy by performing scan-in operations for multiple DUTs in parallel across different test channels, then sequentially performing scan-out operations. This dimensional approach allows simultaneous loading of multiple devices while maintaining dedicated test channels for each device during critical measurement phases, effectively resolving the contradiction between channel reduction and throughput maintenance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If more test channels are allocated to handle IC devices with more IO pins, then test coverage is maintained, but capital cost of test system increases

Engineering Contradiction:
Improvetest coverageVSAvoidnumber of test channels
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the testing workflow into a parallel scan-in phase that loads test data into multiple DUTs simultaneously using available test channels, followed by sequential scan-out phases that ensure complete test coverage for each device. This segmentation enables the system to handle devices with more IO pins by efficiently utilizing the limited test channels during the loading phase while maintaining comprehensive coverage during the measurement phase.

Inventive Principle:
Principle #1Segmentation

3Loss of information

If scan test is performed twice to collect all device response data from multiplexed IO pin groups, then all data is captured, but test time is doubled

Engineering Contradiction:
Improvedevice response data collectionVSAvoidscan test time
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The patent segments the data collection process by performing scan-in operations for multiple DUTs in parallel during a single phase, then performing individual scan-out operations for each device. This ensures that all device response data is captured in one test cycle rather than requiring two separate test executions, thereby eliminating the time penalty associated with conventional multiplexing approaches.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10114075B2Scan test multiplexing
Publication Date: 2018.10.30 ADVANTEST CORP
  • US10114075B2 patent drawing
  • US10114075B2 patent drawing
  • US10114075B2 patent drawing

AI summary

System and method for performing scan test on multiple IC devices by site-multiplexing. Multiple test sites of an ATE are coupled to multiple DUTs through a multiplexer. A scan test includes a scan-in/out phase and consecutive launch/capture cycles. Each site performs scan in/out in parallel on the corresponding DUT. In each launch/capture cycle, a respective site drives/captures data from a DUT while the remaining sites are inactive. The multiplexer allows the active site to borrow test channels assigned to other test sites such that all the test data of a DUT can be driven/captured in the launch capture cycle despite the test channel limitation of the active test site. As the tester channels receive interleaved data of the multiple sites, each strobe edge of a receive channel is assigned to a particular test site and used to quickly identify a failure site without post-processing test data.