Scan Test Output Isolation for Lower-Power Integrated Circuits
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Solution Overview
Problem
Conventional semiconductor integrated circuits face high power consumption during normal operation due to the presence of test-only paths that are not isolated, leading to increased energy usage even during non-test operations, especially in large-scale logic circuits.
Innovation Solution
The introduction of a semiconductor integrated circuit design with independently operating first and second signal output units, where the second unit is halted during normal operations, isolating the scan test circuit configuration to prevent power consumption issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a scan test function is introduced to enable testing of large scale logic circuits, then test capability is improved, but power consumption during normal operation increases
Solution Approach 1:
The patent divides the signal output functionality into two independent units: a first signal output unit for normal operation and a second signal output unit for scan test operation. This segmentation allows each unit to operate independently, enabling the test circuit to be isolated during normal operation and thus eliminating the power consumption issue while maintaining test capability.
Solution Approach 2:
The patent implements dynamic control of the scan test circuit through a control signal that selectively activates or deactivates the second signal output unit. During normal operation, the second unit is deactivated to minimize power consumption, while during test operations, it is activated to provide test functionality. This dynamic switching resolves the contradiction between maintaining test capability and reducing operational power consumption.
2Speed
If delay circuits are inserted to the test-only path to adjust timing, then timing adjustment capability is improved, but power consumption increases
Solution Approach 1:
The patent segments the timing control functionality from the normal operation path by placing delay circuits exclusively in the second signal output unit's path. This allows timing adjustment to be performed only when needed for test operations, while the first signal output unit maintains normal operation without unnecessary delay circuits, thereby reducing overall power consumption.
Solution Approach 2:
The patent dynamically controls the activation of delay circuits in the test-only path through the same control signal mechanism. The delay circuits are activated only during scan test operations when timing adjustment is required, and deactivated during normal operation, thus providing timing adjustment capability only when needed while minimizing power consumption during normal operation.
3Reliability
If the test-only path is branched from the primary path of the flip-flop, then test path isolation is improved, but operating power consumption exists during normal operation
Solution Approach 1:
The patent fully segments the test path from the primary path by creating a completely separate second signal output unit that is only activated during test operations. The branching is enhanced with a control mechanism that ensures the test-only path is electrically isolated during normal operation, eliminating leakage current and operating power consumption in the test path while maintaining structural isolation for test capability.
Solution Approach 2:
The patent introduces a control signal as an intermediary mechanism that manages the activation state of the second signal output unit. This control intermediary ensures that the test-only path is completely deactivated during normal operation, preventing any power consumption in the isolated path while maintaining the structural separation needed for test path isolation during actual test operations.
Data Source
AI summary
The present invention provides a semiconductor integrated circuits that can prevent causes arising a problem of the power consumption during the normal operation thereof. Solution: The present invention relates to a semiconductor integrated circuit having a plurality of memory device of the scan thereof having functions to output the status values during the scan test therein. At least, a part of the memory device of the scan includes a first signal-outputting unit outputting a signal during the normal operation therein and a second signal-outputting unit outputting a signal during the scan test operation therein, respectively. Where, it is preferable that the first signal-outputting unit has a larger driving capacity to signal lines therein than the second signal-outputting unit, and that a second signal-outputting unit fixes the output signal level during the normal operation thereof, and that the second signal-outputting unit outputs a status value delayed a predetermined period of the operation clock therein compared with the first signal-outputting unit during the scan test thereof, and so on.