Scan Test Pattern Compression via X-Tolerant Unload Selector
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Solution Overview
Problem
In automatic test pattern generation for integrated circuits, existing methods face challenges in efficiently managing load/unload conflicts in scan test architectures, leading to reduced test data compression and increased design complexity due to the need for extra input pins and state elements.
Innovation Solution
A method is introduced to generate scan-based test patterns that resolve conflicts by managing detection needs globally, linking multiple dynamic streams of test patterns, and using an unload selector with X-tolerant modes to ensure observability without additional input pins or state elements, thereby reducing padding patterns and enhancing test data compression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If existing methods are used to manage load/unload conflicts in scan test architectures, then test patterns can be generated, but test data compression is reduced and design complexity increases due to extra input pins and state elements
Solution Approach 1:
The patent extracts and eliminates the unnecessary padding patterns from the test pattern generation process. By identifying that padding patterns are not required for proper functionality, the invention removes this extra element, thereby reducing design complexity without compromising test data compression capabilities
Solution Approach 2:
The unload selector is designed to automatically manage load/unload conflicts using X-tolerant modes without requiring external control inputs. The system self-regulates the test pattern loading and unloading processes, eliminating the need for additional input pins and state elements that would otherwise be required to manage these conflicts
2Reliability
If padding patterns are used to resolve load/unload conflicts, then observability is maintained, but test application time increases
Solution Approach 1:
The patent removes padding patterns from the test pattern sequence while maintaining observability through the X-tolerant unload selector. By extracting the unnecessary padding elements, the test application time is reduced without sacrificing the ability to observe test responses
Solution Approach 2:
The unload selector dynamically adapts its operation based on the presence of unknown values (Xs) in the test patterns. By switching between different X-tolerant modes, the system maintains observability for valid patterns while efficiently skipping or handling patterns with excessive unknowns, thereby reducing overall test application time
3Reliability
If multiple streams of test patterns are managed dynamically, then detection needs are satisfied globally, but pattern generation complexity increases
Solution Approach 1:
The patent merges multiple dynamic streams of test patterns into a unified global detection framework. By combining the management of multiple streams under a single unload selector with X-tolerant modes, the system satisfies detection needs globally while avoiding the complexity of managing each stream independently
Solution Approach 2:
The unload selector is designed as a universal component that handles multiple functions: managing load/unload conflicts, satisfying detection needs across multiple test pattern streams, and maintaining observability. This multi-functional approach reduces overall system complexity compared to having separate dedicated components for each function
Data Source
AI summary
A method for generating scan-based test patterns for an integrated circuit design includes, in a computer system, generating a number of current interval patterns for the integrated circuit design in a current pattern generation interval. The current interval patterns can be augmented to satisfy observe needs of a previous interval pattern generated in a previous pattern generation interval. Observe needs of the current interval patterns are stored in association with the current interval patterns. The current interval patterns are linked respectively to P streams of test patterns. The current pattern generation interval is subsequent to the previous pattern generation interval. The method includes simulating the current interval patterns to identify observable scan cells in the integrated circuit design, linking the P streams of test patterns into a single stream of test patterns, and storing the single stream of test patterns in a computer readable medium.