Scan Test Simulation Using Dual-Path Memory Elements
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Solution Overview
Problem
Current methods for simulating scan tests in integrated circuits require substantial computational and memory resources, particularly due to unneeded evaluations in the combinational logic during the shift phase of scan tests.
Innovation Solution
The introduction of new memory elements with two paths, where one path connects data to combinational logic only during the capture phase and the other path connects data to the next element in the chain during the shift phase, reduces resource requirements by minimizing unneeded transitions and evaluations in the combinational logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory elements are replaced with new elements having two paths during scan test simulation, then resource requirements are reduced, but device complexity increases
Solution Approach 1:
The memory element is segmented into two distinct paths: a first path for connecting data output to combinational logic during capture phase, and a second path for connecting to the next memory element during shift phase. This segmentation allows the simulation to selectively activate only necessary paths, reducing unnecessary computational evaluations while maintaining functional correctness
Solution Approach 2:
The memory element structure is made dynamic by enabling different paths based on the operational phase. During capture phase, the first path is activated to feed combinational logic; during shift phase, the second path is activated to shift data through the scan chain. This dynamic path selection optimizes simulation resources by avoiding evaluations of inactive paths
2Measurement precision
If additional circuitry is added to memory elements for simulation, then scan test simulation accuracy improves, but fabrication delays increase
Solution Approach 1:
A copied version of the memory element with enhanced two-path circuitry is created specifically for simulation purposes. This copied structure enables accurate scan test simulation by properly modeling the capture and shift phases. The original design without these modifications is preserved for fabrication, ensuring no additional delays are introduced in the actual hardware
Solution Approach 2:
The simulation model uses modified parameters and structures (the two-path memory element) that accurately represent scan test behavior. By changing the simulation parameters to include these specialized paths, the simulation achieves higher precision in measuring scan test performance without requiring the actual fabricated circuit to include the additional circuitry
Data Source
AI summary
An aspect of the present invention replaces memory elements in a scan chain with corresponding new (memory) elements, with each new element having two paths to provide the corresponding data output. One of the two paths is operable to connect the data value to the combinational logic only during a capture phase of said test mode, and the second path is operable to connect the data value to the next element in the chain during a shift phase of said test mode. As a result, unneeded transitions/evaluations in the combinational logic are avoided during shift time, thereby reducing the resource requirements in the corresponding duration. However, the further processes (including various design phases and fabrication) are continued based on the original data (i.e., without the new elements) such that unneeded delays are avoided during the eventual operation in functional mode of the various fabricated IC units.