Scan Testing Logic Device Defect Segmentation
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Solution Overview
Problem
Traditional semiconductor manufacturing techniques result in defects in logic devices like SIMDs, which can render devices inoperable, and existing methods are inefficient in testing and compensating for these defects, particularly in critical processing functions.
Innovation Solution
A method involving the comparison of test patterns with inputs and outputs from logic device sub-modules to identify and classify defects, using redundant and non-redundant logic areas, and employing automated test equipment to facilitate defect tolerance and compensation, including the use of e-fuses for fail-safe mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional semiconductor manufacturing techniques are used, then chips are produced with inherent defects due to impurities, but defect detection and compensation methods are inefficient
Solution Approach 1:
The logic device is divided into multiple scan chains, each comprising several logic device sub-modules. This segmentation allows independent testing of each scan chain, enabling efficient identification of defective sub-modules without testing the entire device at once, thus resolving the contradiction between reliability assessment and manufacturing efficiency
Solution Approach 2:
The patent performs scan testing during the manufacturing process to identify defects before final device assembly and deployment. By conducting preliminary defect detection and classification, the system can compensate for defects early in the manufacturing流程, improving both reliability assurance and manufacturing efficiency through early intervention
2Reliability
If redundant sub-modules are included in SIMDs to compensate for defects, then defect tolerance is improved, but device complexity increases
Solution Approach 1:
The patent implements different testing and compensation strategies for different types of logic device sub-modules based on their criticality. Critical sub-modules that render the device inoperable when defective receive priority testing and compensation, while non-critical sub-modules use standard compensation methods. This localized quality approach improves defect tolerance for critical functions without uniformly increasing complexity across the entire SIMD architecture
Solution Approach 2:
The system dynamically adjusts compensation parameters based on the type and severity of defects detected during scan testing. By changing compensation parameters rather than always activating full redundancy, the system achieves effective defect tolerance while minimizing the actual complexity overhead in normal operation
3Measurement precision
If comprehensive testing of all logic device sub-modules is performed, then defect identification accuracy is improved, but testing time and complexity increase
Solution Approach 1:
The logic device is divided into multiple scan chains that can be tested independently and in parallel. This segmentation allows the testing system to process multiple sub-modules simultaneously, maintaining high defect identification accuracy while reducing total testing time through parallel execution of tests on different scan chains
Solution Approach 2:
The patent performs comprehensive testing on critical sub-modules that render the device inoperable when defective, while using expedited or representative testing on non-critical sub-modules. This partial action approach focuses testing resources on the most important areas, achieving sufficient defect identification accuracy for device operability without the time cost of exhaustive testing of every single sub-module
Data Source
AI summary
Provided is a method of testing a logic device. The method includes comparing a first test pattern provided at an input of a first chain of logic device sub-modules with an output from the first chain to determine first type failures and comparing a second test pattern provided at an input of a second chain of logic device sub-modules with an out from the second chain to determine second type failures. An occurrence of one of the first type failures renders the logic device inoperable. An occurrence of the second type of failures is tolerated.