Scan Testing Power-Shutoff Architecture for IC Reliability
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Solution Overview
Problem
Scan testing for ICs is power-intensive, leading to potential false failures and increased manufacturing costs due to excessive power consumption, especially during scan shifting and timed tests, where conventional methods do not incorporate power-shutoff aware features.
Innovation Solution
The implementation of a method that configures circuit elements into power domains with separate power controls, including an always-on domain and independent power domains that can be powered off, using decompressor and compressor circuits, isolation circuits, and masking logic to manage power levels and reduce power consumption during scan testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan testing is performed with high switching activity, then test coverage is improved, but power consumption increases causing voltage droop and false failures
Solution Approach 1:
The chip is divided into multiple power domains with independent power control, allowing selective shutdown of unused domains during scan testing. Each power domain can be independently managed to reduce overall power consumption while maintaining test functionality in active domains.
Solution Approach 2:
Power domains are dynamically controlled during scan testing, with the ability to switch between power-on and power-off states based on testing requirements. This dynamic power management allows the system to adapt power consumption to actual testing needs, reducing voltage droop while maintaining test coverage.
2Reliability
If scan speed is reduced to lower power consumption, then power-related false failures are reduced, but test time increases
Solution Approach 1:
By segmenting the chip into power domains, the system can maintain high scan speeds in active domains while shutting down unused domains, avoiding the need to reduce overall scan speed. This preserves test time while reducing power consumption through selective domain shutdown.
Solution Approach 2:
Different power domains can operate at different power states simultaneously, allowing high-speed testing in active regions while low-power mode is maintained in inactive regions. This local differentiation resolves the contradiction by applying different operational characteristics to different parts of the system.
3Use of energy by moving object
If power-shutoff features are incorporated during scan testing, then power consumption is reduced, but test architecture complexity increases
Solution Approach 1:
The chip is divided into multiple power domains with independent power control, allowing selective shutdown of unused domains during scan testing. Each power domain can be independently managed to reduce overall power consumption while maintaining test functionality in active domains.
Solution Approach 2:
Isolation circuits are introduced as intermediary elements between power domains and scan chains. These isolation circuits manage the interaction between power shutdown and scan testing, ensuring proper signal isolation and domain separation while simplifying the overall control architecture.
Data Source
AI summary
In a circuit adapted for scan testing, a first set of connections configures the circuit elements into power domains with separate power-level controls, and a second set of connections configures the circuit elements to form scan segments for loading values into circuit elements from input ends of the scan segments and unloading values from circuit elements at output ends of the scan segments. A decompressor circuit receives a decompressor input and is operatively connected to the scan-segment input ends, and a compressor circuit is operatively connected to the scan segment output ends and generates a compressor output. Isolation circuits at scan-segment exits set values for scan segments at scan-segment exits when a corresponding independent power domain is in a power-off state.