Scan Testing System Parallel Chains Oversampling
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Solution Overview
Problem
As integrated circuits grow in size, the complexity of scan chains during scan-based testing increases, leading to higher memory requirements and longer test times due to the need for more shift cycles and physical bandwidth, while high X-density during testing can render compression algorithms ineffective, masking data and faults.
Innovation Solution
The implementation of a system with multiple parallel scan chains and a compressor network that oversamples scan chain output signals, allowing for increased data capture and reduction of X-density by staggering scan chain outputs and using multiple clock signals to sample data at different times, thereby improving compression ratios without increasing X-density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If parallel scanning is implemented to reduce shift cycles, then test time is reduced, but the number of I/O pins required increases
Solution Approach 1:
The patent divides the scan chain into multiple parallel scan chains, each independently operable. This segmentation allows simultaneous testing of multiple data paths, reducing the total number of shift cycles required and thereby reducing test time while managing I/O pin requirements through efficient parallelization.
Solution Approach 2:
The patent introduces a temporal dimension by oversampling scan chain outputs multiple times within a single clock cycle. This allows multiple data captures from the same physical I/O pins at different time instances, effectively increasing data throughput without proportionally increasing the number of physical pins required.
2Reliability
If scan chain size is increased to handle larger circuits, then coverage is improved, but memory requirements and test time increase
Solution Approach 1:
The patent segments the large scan chain into multiple smaller parallel scan chains. Each chain handles a portion of the circuit under test, reducing the data volume that must be stored in memory while maintaining comprehensive coverage through the parallel structure. This segmentation directly reduces memory requirements proportional to the number of chains.
Solution Approach 2:
The patent employs periodic oversampling of scan chain outputs, capturing data multiple times within a clock cycle. This periodic action allows efficient use of memory by capturing multiple data points from the same physical locations without requiring proportional increases in memory capacity, as the same memory resources are reused across multiple capture cycles.
3Quantity of substance
If compression algorithms are used to reduce data volume, then memory requirements are reduced, but X-density masks data and faults
Solution Approach 1:
The patent performs preliminary oversampling of scan chain outputs before compression. By capturing multiple data points in advance and storing them in a buffer, the system prepares clean, reliable data that can be compressed without the harmful effects of X-density. This preliminary action separates the compression operation from the data capture, allowing compression to proceed on purified data.
Solution Approach 2:
The patent introduces an intermediary buffer between the scan chain outputs and the compression algorithm. This buffer temporarily stores the oversampled data, acting as a mediator that filters out X-density effects before the data enters the compression pipeline. The buffer allows compression to operate on clean data while the scan chains continue their periodic oversampling operation.
Data Source
AI summary
A system including a first clock, a first scan chain, and a first sampling circuit. The first clock is configured to generate a first clock signal. The first scan chain includes a first input, a first set of devices, and a first output. The first input is configured to receive a portion of first data to test the first scan chain. The first set of devices has a first plurality of states, wherein each of the first set of devices changes between the first plurality of states in response to the portion of the first data. The first output is configured to output a portion of second data in response to the first plurality of states. The first sampling circuit is configured to sample the portion of the second data from the first output at least twice per clock cycle of the first clock signal.