Scan Warmup Unit Mitigates Di/dt During Integrated Circuit Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
During the testing of semiconductor processors, the sudden discharge of chip capacitance due to a global scan signal can lead to an excessive current draw, causing a voltage drop and potential operational errors, making it difficult to determine the maximum voltage and frequency at which the processor is operable.
Innovation Solution
A localized scan shift enable signal is generated, allowing for a controlled transition from a test clock frequency to a system clock frequency, reducing the change in current draw and mitigating voltage drops through a scan warmup unit that adjusts the scan clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a global scan signal is applied and de-asserted with a long time interval before the master clock signal, then the chip capacitance has sufficiently discharged allowing proper testing, but an excessive current draw occurs causing voltage drop and potential operational errors
Solution Approach 1:
The scan warmup unit performs preliminary clock frequency adjustment before the actual scan test. It transitions the scan clock from test frequency to system clock frequency in a controlled manner, preparing the circuit to avoid excessive current draw when the global scan signal is de-asserted, thereby preventing voltage drop while maintaining testing accuracy
Solution Approach 2:
The scan clock frequency is made dynamic rather than static. The scan warmup unit adjusts the scan clock frequency from the test frequency to the system clock frequency based on the timing of the global scan signal de-assertion, creating an adaptive timing mechanism that prevents di/dt events while ensuring proper test conditions
2Productivity
If the scan clock frequency is transitioned from test frequency to system clock frequency, then the processor can be tested at operating conditions, but a sudden change in current draw occurs causing voltage drop
Solution Approach 1:
The scan warmup unit performs preliminary frequency transition before the main scan test operation. It gradually adjusts the scan clock from test frequency to system clock frequency, spreading out the current draw over time rather than causing a sudden spike, thereby maintaining testing efficiency while controlling power consumption
Solution Approach 2:
The frequency transition is performed in a controlled periodic manner through the scan warmup unit, which adjusts the scan clock frequency in steps or over a defined time period rather than instantaneously, reducing the peak current draw while still achieving the necessary testing conditions
Data Source
AI summary
We report methods relating to scan warmup of integrated circuit devices. One such method may comprise loading a scan test stimulus to and unloading a scan test response from a first set of logic elements of an integrated circuit device at a scan clock first frequency equal to a test clock frequency; adjusting the scan clock from the first frequency to a second frequency by a scan warmup unit, wherein the scan clock second frequency is equal to a system clock frequency; and capturing the scan test response by a shift logic at the scan clock second frequency. We also report processors containing components configured to implement the method, and fabrication of such processors. The methods and their implementation may reduce di/dt events otherwise commonly occurring when testing logic elements of integrated circuit devices.