Scan Wrapper Circuit for Multi-Partition SoC Test Control
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Solution Overview
Problem
Modern integrated circuits face challenges in achieving comprehensive scan test coverage for multi-partition SoC systems due to pin limitations, power consumption, and timing constraints, leading to inefficiencies in test access and increased test times.
Innovation Solution
A scan wrapper architecture that configures each partition with separately controllable INTEST and EXTEST scan chains, using digital test control access hardware with AND gating circuitry to load constant scan data and generate separate launch-off-shift scan enable signals, allowing for efficient scan testing without additional test logic overhead or timing degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan testing is performed on multi-partition SoC systems using conventional methods, then test coverage can be achieved, but pin limitations and timing constraints prevent comprehensive testing while increasing test time
Solution Approach 1:
The patent divides the scan testing into separate INTEST and EXTEST modes that can be independently controlled for each partition. This segmentation allows different scan chains to be activated selectively, enabling comprehensive testing of multi-partition SoC systems without requiring all partitions to be tested simultaneously, thus reducing overall test time while maintaining complete test coverage.
Solution Approach 2:
The patent implements dynamic control of scan chains through separately controllable scan enable signals (SE_INT for INTEST mode and SE_EXT for EXTEST mode). This dynamic control allows the testing system to adaptively activate only the necessary scan chains based on the current test mode and partition being tested, optimizing test time utilization and avoiding the bottleneck of testing all partitions concurrently.
2Productivity
If additional test logic is added to enable separate control of scan chains, then scan testing efficiency improves, but device complexity increases
Solution Approach 1:
The patent merges the control functions for INTEST and EXTEST scan chains into a unified scan wrapper architecture. By combining the control logic at the wrapper level rather than adding separate control logic for each scan chain, the design achieves separate controllability of scan chains while minimizing the increase in device complexity. The merged approach allows efficient scan testing through coordinated control of multiple scan chains without proportionally increasing test logic overhead.
3Productivity
If scan data is shifted into all scan chains simultaneously, then testing can proceed in parallel, but power consumption increases
Solution Approach 1:
The patent implements partial action by allowing selective activation of scan chains based on the current test mode. In INTEST mode, only INTEST scan chains are activated while EXTEST scan chains remain inactive, and vice versa. This partial activation approach enables parallel testing of necessary scan chains while avoiding the excessive power consumption that would result from shifting data into all scan chains simultaneously, thus optimizing the balance between testing parallelism and power consumption.
Data Source
AI summary
An apparatus and method are provided for scan testing a system-on-chip (SoC) integrated circuit having first and second partitions coupled together across one or more inter-partition circuits, each of which includes a decompressor; a compactor; an INTEST scan chain and an EXTEST scan chain coupled in parallel between the decompressor circuit and compactor circuit; and digital test control access hardware connected between the decompressor circuit and each INTEST scan chain and configured to selectively disable each INTEST scan chain while each EXTEST scan chain continues to operate in response to a partition EXTEST mode signal having a first predetermined value.