Scan Wrapper Architecture for SoC Test Pin Reduction
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Solution Overview
Problem
Existing system-on-chip (SoC) test architectures face limitations in achieving high test coverage due to limited input/output pins, requiring a large number of test combinations and increasing test time, especially in the external test (EXTEST) mode.
Innovation Solution
The proposed SoC architecture includes a configuration with input and output channels, partitions, and inter-partition circuits that allow for reduced input/output pin requirements by storing intermediate data unobserved in the EXTEST mode, enabling the generation of test response data and output test data without dedicated observation or control pins, thus allowing more partitions to be tested simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the SoC uses limited input/output pins for testing, then the device complexity is reduced, but the test coverage and productivity deteriorate due to the need for a large number of test combinations
Solution Approach 1:
The SoC is divided into multiple partitions, each with dedicated wrapper chains. The wrapper chains are segmented into input wrapper chains and output wrapper chains, allowing independent control and observation of each partition's interface. This segmentation enables parallel testing of multiple partitions using the same physical pins, thereby improving test coverage without increasing pin count.
Solution Approach 2:
The wrapper chains serve multiple functions: they act as input buffers for test data, output buffers for test responses, and isolation barriers between partitions. The same physical pins are reused across different partitions and test cycles, enabling universal utilization of limited I/O resources to achieve comprehensive test coverage.
2Productivity
If more partitions are tested simultaneously, then the test productivity improves, but the device complexity increases due to additional wrapper chains and inter-partition circuits
Solution Approach 1:
Multiple wrapper chains are merged into a unified wrapper architecture that shares common control logic and inter-partition circuits. The input wrapper chains and output wrapper chains are integrated into a cohesive structure that can be controlled through standardized interfaces, reducing the overall complexity despite supporting multiple partitions.
Solution Approach 2:
The wrapper chains are organized in a hierarchical structure with multiple dimensions: individual chain level, partition level, and SoC level. This multi-dimensional organization allows parallel operation of multiple partitions while maintaining manageable complexity through hierarchical control and abstraction.
3Measurement precision
If dedicated observation pins are used for intermediate data, then the measurement precision improves, but the loss of substance increases due to additional pin requirements
Solution Approach 1:
The output wrapper chains act as intermediaries that buffer and hold intermediate test data without requiring direct observation pins. The wrapper chains serialize and store intermediate data internally, allowing subsequent access through the existing output pins, thereby eliminating the need for dedicated observation pins while maintaining measurement capability.
Solution Approach 2:
The wrapper chains perform preliminary data buffering and serialization before data leaves the partition. Intermediate data is captured and held in the wrapper chains in advance, allowing comprehensive observation and analysis without requiring additional pins during the actual test operation.
Data Source
AI summary
A system-on-chip (SoC) is disclosed. The SoC includes a set of input channels, a first partition including a set of output wrapper chains, a set of output channels, a second partition including a set of input wrapper chains, and an inter-partition circuit coupled between the first and second partitions. During an external test mode, the set of input channels receives input test data. The set of output wrapper chains receives and stores intermediate data that is generated based on the input test data. The inter-partition circuit receives the intermediate data from the set of output wrapper chains and generates test response data based on the intermediate data. The set of input wrapper chains receives the test response data, and provides the test response data to be captured as output test data at the set of output channels to test the inter-partition circuit.