Scan Synchronous-Write-Through Testing Architecture for Memory Faults

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Solution Overview

Problem

Existing memory devices face challenges in efficiently identifying and addressing manufacturing faults during testing, particularly in scenarios where multiple devices are interconnected, leading to inefficiencies in fault detection and diagnosis.

Innovation Solution

A testing environment that operates in shift, capture, and scan modes to deliver serial and parallel data sequences to memory devices, enabling comprehensive fault detection through scan synchronous-write-through (SWT) testing, utilizing multiplexing and latching circuits to synchronize data flow and enhance fault detection capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If comprehensive testing of interconnected memory devices is performed, then fault detection capability is improved, but testing time and complexity increase

Engineering Contradiction:

Improvefault detection capabilityVSAvoidtesting time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The testing architecture segments the interconnected memory devices into individual testable units with separate test interfaces. Each memory device can be tested independently through its own test mode interface, allowing parallel testing of multiple devices without requiring sequential testing of the entire interconnected system, thus reducing total testing time while maintaining comprehensive fault detection capability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces test mode interfaces and control logic as intermediary components between the test signals and the memory devices. These intermediaries facilitate efficient test signal distribution and response collection, enabling comprehensive testing of fault detection capabilities while reducing the complexity of direct device-to-device testing interactions

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If comprehensive testing of interconnected memory devices is performed, then fault detection capability is improved, but device complexity increases

Engineering Contradiction:

Improvefault detection capabilityVSAvoidtesting architecture complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The testing architecture employs universal test mode interfaces and control logic that can be applied to any memory device in the interconnected system. The same test infrastructure and control mechanisms serve multiple devices simultaneously, reducing overall system complexity compared to having dedicated testing circuits for each device, while maintaining comprehensive fault detection capability across all devices

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Measurement precision

If all circuitry remains active during testing, then testing accuracy is maintained, but power consumption increases

Engineering Contradiction:

Improvetesting accuracyVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The memory devices dynamically switch between operational modes and test modes during the testing process. Non-essential circuitry is selectively disabled or placed in low-power states when not required for specific test operations, while essential testing circuits remain active. This dynamic power management maintains testing accuracy for active components while significantly reducing overall power consumption during the testing process

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS12436858B2Scan synchronous-write-through testing architectures for a memory device

Publication Date: 2025.10.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.