Scannable Memory Array Testing via Multiplexer Integration
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Solution Overview
Problem
Current memory built-in self-test (MBIST) technologies are expensive due to the need for an on-chip test controller and are typically performed after initial scan tests, leading to longer test times and higher costs, with no existing solutions for creating scannable memory arrays that can efficiently test SRAM cells and latches like flip-flops.
Innovation Solution
The technology makes memory arrays scannable by incorporating a scan chain that allows for the full control and observation of memory array contents, enabling efficient scan testing of SRAM cells and latches without the need for traditional architectures, thereby catching errors such as stuck-at faults and transition timing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional MBIST architecture is used, then memory testing capability is provided, but test cost and test time increase due to on-chip test controller requirements
Solution Approach 1:
The memory array is designed to serve dual purposes: normal memory operation and scan testing. By making the memory array itself scannable through multiplexer integration, the same hardware structure performs both storage and self-testing functions, eliminating the need for separate dedicated test controllers and reducing overall device complexity.
Solution Approach 2:
The memory array performs its own testing by utilizing its internal structure and multiplexers to enable scan operations. The memory cells themselves are configured to allow scan input and output operations, enabling the memory to self-test without external specialized testing equipment or controllers.
2Reliability
If traditional MBIST is performed after initial scan tests, then comprehensive memory testing is achieved, but overall test time increases
Solution Approach 1:
The invention merges the scan testing capability with memory testing by making the memory array scannable. This integration allows a single unified testing approach that combines the benefits of scan testing (early failure detection, simplicity) with memory testing (comprehensive coverage), eliminating the need for sequential execution of separate test sequences and reducing overall test time.
3Ease of operation
If memory arrays are made scannable with individual multiplexers per cell, then full scan control and observation is enabled, but device complexity and area increase
Solution Approach 1:
The scan functionality is segmented and integrated at the memory cell level through multiplexers that are part of the memory cell structure. Each memory cell includes multiplexers that enable scan operations, allowing the scan function to be distributed throughout the memory array rather than requiring centralized complex control logic, thus enabling full scan control while managing complexity through modular integration.
Data Source
AI summary
A method is disclosed for scanning an array of memory cells arranged in rows and columns, where the array includes a scan chain partitioned into multiple sections. Each section includes a first scan multiplexer, a section buffer cell, and multiple memory cells. The method includes determining whether a scan shift mode is entered, asserting a scan enable signal to select second inputs of each first scan multiplexer when the scan shift mode is entered, coupling the scan input with the input of the section buffer cell of the first section, and coupling the output of the memory cell in the previous section with the input of the section buffer cell in the next section. The method further includes updating the contents of the section buffer cell and the memory cells using clock signals and scan word line pulses.