Scannable Memory Array Modes for High-Density IC Testing
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Solution Overview
Problem
Integrated circuits face challenges in efficiently testing high-density memory circuits due to limited testability, particularly in complex and high-speed environments.
Innovation Solution
The integration of scannable memory circuits with storage elements like latches into scan chains, enabling efficient testing through mechanisms such as scan dump and ATPG, by using a control circuit to manage scan enable signals and row addresses, allowing data to be loaded and outputted in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional memory testing methods are used, then testing can be performed, but testability is limited and testing efficiency is low
Solution Approach 1:
The memory circuit is designed to perform both functional operations and test operations using the same hardware resources. The scan chain can be used for both normal data transfer and test pattern injection, while the memory array serves both storage and testable storage functions. This multi-functionality improves testing efficiency without proportionally increasing circuit complexity.
Solution Approach 2:
A scan chain is introduced as an intermediary structure that enables test pattern generation and response collection. The scan chain acts as a mediator between external test equipment and the internal memory circuitry, allowing ATPG and other testing methodologies to function effectively without requiring fundamental changes to the memory architecture.
2Quantity of substance
If high-density memory circuits are used, then memory capacity increases, but testability decreases
Solution Approach 1:
The high-density memory array is segmented into smaller, testable units that can be individually accessed and tested through the scan chain. By dividing the large memory structure into manageable blocks with controlled access paths, the patent maintains high overall density while improving testability through systematic decomposition of the testing task.
Solution Approach 2:
The patent introduces a temporal dimension to testing by using clocked scan operations. Instead of attempting to test all memory elements simultaneously (spatial approach), the scan chain enables sequential testing over time, allowing comprehensive testing of high-density memory without requiring proportional increases in test complexity.
3Difficulty of detecting and measuring
If scan chains are integrated into memory circuits, then testability improves, but circuit area increases
Solution Approach 1:
The scan chain functionality is merged with the existing memory interconnect and control logic. By combining test functions with functional paths, the patent avoids duplicating infrastructure and minimizes the additional area required for test capabilities. The same wiring and control mechanisms serve both operational and testing purposes.
Solution Approach 2:
Existing memory circuit components are designed to serve multiple functions: data storage, data transfer, and test pattern propagation. This multi-functionality reduces the need for dedicated test-only hardware, thereby limiting the increase in circuit area while still achieving improved testability through scan chain integration.
Data Source
AI summary
An integrated circuit (IC) includes a memory array with M rows of N storage elements that has an N-bit wide parallel input and output, and a 1-bit wide array scan input and output. A memory built-in self-test (MBIST) circuit is connected to the memory array to generate test addresses and N-bit wide test data. Functional circuitry with a functional address bus and N-bit wide functional data path is linked to the memory array. Control circuitry enables a serial test mode for shifting data through the storage elements, a MBIST mode for test data access, and a normal operation mode for functional data access. This IC design offers versatile memory testing and operational capabilities.