Scannable Storage Circuit for Low-Power ATPG Shift
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Solution Overview
Problem
Integrated circuit (IC) testing faces high static timing analysis closure frequency in automatic test pattern generation (ATPG) shift mode due to high IR drop and reliability issues, leading to increased power consumption and test time, especially in combinational logic toggling during ATPG shift, which is unnecessary and causes battery discharge in overdrive modes.
Innovation Solution
A scannable storage circuit design with a data output buffer incorporating MOS transistors and control signals to selectively pull up or pull down data and scan outputs, allowing for dynamic control of power consumption and minimizing unnecessary toggling during ATPG shift and functional operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan data is transferred through standard flip-flops with multiplexors in ATPG shift mode, then test coverage is achieved, but power consumption increases and frequency is limited due to complete design logic toggling
Solution Approach 1:
The invention segments the scan path into two separate paths: a functional scan path for test coverage and a collapsed scan path for ATPG shift operations. The collapsed scan path merges multiple flip-flops into a single equivalent flip-flop per logic block, eliminating unnecessary toggling in combinational logic while maintaining test coverage capabilities.
Solution Approach 2:
The invention introduces a scan path selection mechanism that acts as an intermediary to route scan data through different paths based on operational mode. The selection logic directs ATPG shift operations through the collapsed scan path and functional testing through the standard scan path, optimizing power consumption for each mode.
2Productivity
If ATPG shift frequency is increased to reduce test time, then productivity improves, but IR drop and reliability issues worsen due to high current demand
Solution Approach 1:
The collapsed scan path segments the large-scale parallel switching into smaller, localized transitions within each logic block. By collapsing multiple flip-flops into one equivalent flip-flop per block, the invention reduces the overall switching activity and current demand, enabling higher frequencies without excessive IR drop.
3Measurement precision
If functional combinational logic toggles during ATPG shift, then test accuracy is maintained, but power consumption increases unnecessarily
Solution Approach 1:
The invention extracts the essential testing functionality from the full scan path and implements it in the collapsed scan path. By taking out only the necessary state capture function and eliminating the combinational logic toggling that occurs in the full scan path, the invention maintains test accuracy while removing unnecessary power consumption.
4Ease of operation
If standard scan flip-flops are used in functional mode, then data transmission is achieved, but power is wasted when D pin signal activity propagates to SD pins of subsequent flops
Solution Approach 1:
The invention extracts and isolates the scan data transmission function from the functional data path. By using separate scan input terminals and internal routing that bypasses the functional D pin logic, the invention enables scan operations without activating unnecessary functional combinational logic, thereby reducing functional power loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces power consumption and test time by controlling the toggling of combinational logic, optimizing ATPG shift frequency and minimizing battery discharge, while maintaining flexibility for post-silicon configuration to suit various test sequences.
Implementation Method 1
a transmission gate having a first metal oxide semiconductor (MOS) transistor and a second MOS transistor with sources and drains coupled to each other, drains coupled to an output of the inverter and sources coupled to the data output terminal and gates coupled to the scan enable input and an inverted scan enable input
Implementation Method 2
A third MOS transistor and a fourth MOS transistor are coupled to the sources of the first and second MOS transistors, the third MOS transistor and fourth MOS transistor are configured to pull up or pull down the data output terminal in response to a first control signal and a second control signal respectively
Implementation Method 3
The data output buffer includes an inverter; A scan output is generated from the output of the inverter
Data Source
AI summary
A scannable storage circuit includes a scan enable input, a storage element having a Node coupled to a data output buffer for driving a data output terminal. The data output buffer includes an inverter; a transmission gate having a first MOS transistor and a second MOS transistor with sources and drains coupled to each other, drains coupled to an output of the inverter and sources coupled to the data output terminal and gates coupled to the scan enable input and an inverted scan enable input. A third MOS transistor and a fourth MOS transistor is coupled to the sources of the first and second MOS transistors, the third MOS transistor and fourth MOS transistor are configured to pull up or pull down the data output terminal in response to a first control signal and a second control signal respectively. A scan output is generated from the output of the inverter.