Scanner Overlay Correction for Reworked Semiconductor Wafers

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Solution Overview

Problem

In semiconductor processing, maintaining proper alignment between layers during photolithography is challenging due to physical alterations caused by rework processes, such as CMP rework, which affect exposure parameters like wafer scaling coefficients, leading to increased overlay errors.

Innovation Solution

A controller system that differentiates between substrates based on rework processes, applying specific mean corrections to exposure parameters, particularly wafer scaling coefficients, to adjust scanner settings and reduce overlay errors by compensating for the effects of rework processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If rework processes (such as CMP rework) are performed on substrates, then manufacturing flexibility and defect correction capability are improved, but physical alterations to the substrate cause increased overlay errors and reduced alignment precision

Engineering Contradiction:
Improvedefect correction capabilityVSAvoidoverlay alignment precision
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The system performs preliminary identification of reworked substrates using process data before exposure, and pre-calculates the appropriate mean correction values for wafer scaling coefficients. This allows the scanner to be pre-configured with the correct correction parameters, eliminating the negative effects of rework processes on overlay precision.

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If traditional overlay correction methods are used without differentiating reworked substrates, then processing simplicity is maintained, but overlay errors increase due to uncorrected physical alterations from rework

Engineering Contradiction:
Improveprocessing simplicityVSAvoidoverlay accuracy
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

The system automatically identifies reworked substrates using process data from the fabrication process itself, and self-corrects overlay errors by applying appropriate mean corrections to wafer scaling coefficients. This automated approach maintains processing simplicity while significantly improving overlay accuracy compared to manual methods.

Inventive Principle:
Principle #25Self-service

3Manufacturing precision

If mean corrections to wafer scaling coefficients are applied to all substrates, then overlay precision is improved, but unnecessary corrections are applied to non-reworked substrates causing increased process complexity

Engineering Contradiction:
Improveoverlay precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The system applies mean corrections to wafer scaling coefficients selectively only to substrates that have undergone rework processes. By using process data to identify which substrates require correction, the system applies local quality adjustments rather than uniform corrections to all substrates, thereby improving overlay precision without unnecessarily increasing process complexity.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9442392B2Scanner overlay correction system and method
Publication Date: 2016.09.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9442392B2 patent drawing
  • US9442392B2 patent drawing
  • US9442392B2 patent drawing

AI summary

A method of processing first and second semiconductor wafers is provided. Each of the first and second semiconductor wafers has a first layer and a second layer over the first layer. A first lithographic process is performed on the first layer over the first semiconductor wafer using a first inter-field correction and a first intra-field correction. An overlay error of the first lithographic process is determined. A second inter-field correction and a second intra-field correction are computed based on the first inter-field correction, the first intra-field correction, and the measured overlay error. A second lithographic process is performed on the second layer over the second semiconductor wafer, based on the second inter-field correction and the second intra-field correction.