Scanning Signal Line Drive Circuit for TFT Hot Carrier Suppression
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Solution Overview
Problem
The characteristics of thin film transistors (TFTs) in scanning signal line drive circuits, particularly those used in gate driver monolithic panels, deteriorate due to voltage stress, leading to hot carrier degradation and display defects, especially with increasing drive voltages and frequencies in larger display panels.
Innovation Solution
A scanning signal line drive circuit with a shift register configuration that includes cascade-connected unit circuits, utilizing multi-phase clock signals and specific signal supply paths to reduce hot carrier degradation by managing the voltage levels and transitions in TFTs, particularly through the use of oxide semiconductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the drive voltage is increased for high frequency drive, then the drive frequency is improved, but hot carrier degradation of TFT occurs leading to display defects
Solution Approach 1:
The patent applies preliminary action by pre-charging the internal node to a specific voltage level before the reset operation. This preliminary voltage preparation reduces the voltage stress on the TFT during reset transitions, thereby preventing hot carrier degradation while maintaining high frequency drive capability
Solution Approach 2:
The patent changes the voltage parameters dynamically by adjusting the internal node voltage to different levels depending on the operational phase. By controlling the internal node at specific voltage levels during different phases of operation, the patent reduces voltage stress on TFTs during high frequency operation while preventing hot carrier degradation
2Power
If the voltage of GDM circuit is increased for high frequency drive, then the drive frequency is improved, but voltage stress on TFT is increased causing hot carrier degradation
Solution Approach 1:
The patent applies local quality by implementing different voltage levels at different nodes within the circuit. Specifically, the internal node is maintained at optimized voltage levels that reduce stress on specific TFTs, while other parts of the circuit operate at higher voltages necessary for high frequency drive, thereby locally minimizing voltage stress effects
Solution Approach 2:
The patent uses preliminary action by pre-establishing appropriate voltage levels on the internal node before reset operations commence. This preliminary voltage setup ensures that when reset signals are applied, the voltage transitions occur with minimized stress on the TFT, preventing hot carrier degradation even during high power operation
Data Source
AI summary
A scanning signal line drive circuit as a GDM circuit is composed of a plurality of cascade-connected unit circuits and is operated by a multi-phase clock signal in which pulses partially overlap. The nth stage unit circuit includes: an internal node; a diode-connected set transistor connected to a set input terminal; a reset transistor including a drain terminal connected to the internal node, a source terminal connected to a reset state voltage terminal, and a gate terminal connected to the reset input terminal; and an output circuit including an output transistor connected to a clock input terminal and a capacitor, a scanning signal G(n−2), a scanning signal G(n+2), and a scanning signal G(n+1) being supplied to the set input terminal, the reset input terminal, and the reset state voltage terminal, respectively.