Scanning Signal Line Drive Circuit Layout Area Reduction
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Solution Overview
Problem
Conventional active matrix-type display devices face challenges in reducing the picture-frame area due to the increased area required for shift registers, especially in downsizing panels, where the conventional structure of clock signal distribution limits the reduction of wire lines and leads to insufficient protection of the gate driving unit.
Innovation Solution
The scanning signal line drive circuit incorporates multiple shift registers with each stage receiving a part of the clock signals from both the clock signal main lines and adjacent shift registers, reducing the number of wire lines and load capacitance, and utilizing a configuration with four clock signals and phase-displaced clock signals to minimize the layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signals are supplied to each stage of the shift register from clock signal main lines, then the shift register can operate properly, but the area for laying out the shift register increases
Solution Approach 1:
The patent merges the clock signal distribution function into the shift register stages themselves. Each stage receives clock signals from adjacent stages, eliminating the need for separate clock signal main lines. This combining of functions reduces the layout area while maintaining proper operation.
Solution Approach 2:
The shift register stages are designed to serve multiple functions: they process data signals and simultaneously distribute clock signals to adjacent stages. This multi-functionality eliminates the need for dedicated clock distribution infrastructure, reducing the overall layout area.
2Ease of operation
If a large number of clock signals are used to operate the shift register, then the shifting operation can be controlled precisely, but the picture-frame area of the panel increases
Solution Approach 1:
The clock signal distribution is segmented into local portions, where each shift register stage receives clock signals from its adjacent stages rather than from centralized main lines. This segmentation reduces the total number of clock signal lines required across the panel.
Solution Approach 2:
The patent transitions from a centralized clock distribution architecture (requiring multiple main lines across the panel) to a distributed hierarchical architecture where clock signals propagate through the shift register stages themselves, effectively using the data path dimension for clock distribution.
3Area of stationary object
If the area for laying out the shift register is reduced, then the picture-frame area decreases, but the gate driving unit becomes insufficiently protected
Solution Approach 1:
The patent combines the gate driving unit and shift register into a more integrated layout where the shift register stages are positioned adjacent to the gate bus lines they control. This integration allows for reduced overall area while maintaining adequate protection through shared structural elements.
Data Source
AI summary
A gate driver is provided with an odd-numbered stage shift register, an even-numbered stage shift register, and main lines including clock signal main lines. In at least one example embodiment, each stage of one of the shift registers receives the first clock and the second clock from the clock signal main lines, and the third clock and the fourth clock from an adjacently provided stage of the other shift register. Each stage of the shift register can receive the second clock from a different stage of the same shift register. With this, it is possible to reduce a picture-frame area of a panel in a display device provided with a scanning signal line drive circuit having the plurality of shift registers.