Scanning Signal Line Drive Circuit Voltage Fluctuation Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In active-matrix display devices, the scanning signal line drive circuit faces issues with voltage fluctuations due to parasitic capacitance, leading to malfunction and deterioration of TFTs in stabilization circuits, which increases the frame region and reduces reliability, especially under high temperature conditions.
Innovation Solution
A scanning signal line drive circuit with a multiphase clock signal-based shift register configuration, incorporating compensation transistors and circuits that manage voltage levels and reset signals to maintain the internal node at stable logic levels, even in the absence of a functioning stabilization circuit, thereby preventing voltage fluctuations and malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stabilization circuit is added to suppress voltage fluctuations in the internal node, then the reliability of the output transistor is improved, but the frame region increases and manufacturing complexity increases
Solution Approach 1:
The patent combines the stabilization function with the existing shift register unit circuit by making the reset transistor's gate terminal receive the output signal of a succeeding stage unit circuit. This integration eliminates the need for separate stabilization circuits while maintaining voltage suppression functionality, thereby reducing frame region without compromising output transistor reliability.
Solution Approach 2:
The reset transistor in the unit circuit is designed to serve dual purposes: it functions as part of the shift register operation and simultaneously acts as a stabilization element for the internal node. By making the gate terminal of the reset transistor receive the output signal of a succeeding stage, the circuit achieves multi-functionality that suppresses voltage fluctuations without requiring additional dedicated stabilization components.
2Productivity
If the number of unit circuits and wiring lines is increased to improve scanning signal line driving capability, then the display performance is improved, but the frame region increases
Solution Approach 1:
The patent divides the gate driver into multiple unit circuits, each corresponding to a scanning signal line, arranged in a cascade configuration. Each unit circuit is independently structured with transistors and nodes, allowing modular expansion for driving more scanning lines while maintaining compact individual circuit footprints that minimize overall frame region growth.
Solution Approach 2:
The patent implements a nested signal structure where the output signal of each unit circuit serves as the reset signal for the preceding stage unit circuit. This nesting of signal functions within the cascade architecture allows efficient signal propagation and control without requiring additional external wiring lines, thereby improving driving capability while minimizing frame region expansion.
3Reliability
If a stabilization circuit is provided in each unit circuit to prevent voltage fluctuation, then the malfunction prevention is improved, but the device complexity increases
Solution Approach 1:
The unit circuit performs self-stabilization by using its own output signal (from a succeeding stage) to control the reset transistor that suppresses voltage fluctuations at its internal node. This self-service mechanism eliminates the need for external stabilization circuits or additional control signals, maintaining high reliability while minimizing circuit complexity through autonomous operation.
Solution Approach 2:
The patent implements feedback by connecting the gate terminal of the reset transistor to the output signal of a succeeding stage unit circuit. This feedback loop allows the circuit to automatically detect and correct voltage fluctuations at the internal node, ensuring reliable operation without requiring complex external stabilization circuitry or additional control mechanisms.
Data Source
AI summary
A unit circuit constituting each stage of a shift register serving as a gate driver of a display device charges an internal node to an H level via a transistor T2 when an output signal G(n−4) of a preceding stage turns to the H level and sets the internal node to an L level via a transistor T3 when an output signal G(n+8) of a succeeding stage turns to the H level. Each of the unit circuits of last eight stages in the gate driver is provided with a transistor T4 including a gate terminal to which the signal G(n−4) is applied and a drain terminal connected to the internal node. A signal is applied to a source terminal of the transistor T4, the signal being at the H level during a period when the internal node of any of the last eight stages is to be set to the H level, and being the L level during the other periods. This suppresses a voltage fluctuation generated in the internal node when a stabilization circuit does not normally function.