Scatter Gather DMA Descriptor List for Non-Contiguous Memory Transfer
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Solution Overview
Problem
Current Direct Memory Access (DMA) transfer methods are inefficient when dealing with data scattered across non-contiguous memory blocks, as they require significant CPU intervention to manage interrupts and reprogram data transfer control registers, disrupting CPU performance.
Innovation Solution
Implementing scatter/gather DMA, where a CPU creates a chained DMA descriptor list with headers containing source and destination addresses, data lengths, and pointers to next elements, allowing the DMA controller to automatically manage data transfer between non-contiguous blocks without continuous CPU intervention, and enabling the DMA controller to write the 'End of DMA Transfer' message directly, reducing CPU burden.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional DMA transfer methods are used for non-contiguous data blocks, then data transfer can be performed independently of CPU, but CPU intervention is required to manage interrupts and reprogram control registers, disrupting CPU performance
Solution Approach 1:
The patent segments the DMA transfer process into multiple sub-transfers by creating a chained list of DMA descriptors, where each descriptor represents a non-contiguous data block. This allows the DMA controller to handle multiple scattered memory blocks through sequential sub-transfers without requiring CPU intervention between each block transfer.
Solution Approach 2:
The CPU performs preliminary action by setting up the chained DMA descriptor list before the DMA transfer begins. Each descriptor in the chain contains pre-configured source/destination addresses, data lengths, and pointers to the next descriptor. This preliminary configuration enables the DMA controller to autonomously manage the entire scatter/gather transfer process without subsequent CPU intervention.
2Reliability
If CPU manages each DMA interrupt and reprograms control registers, then data transfer accuracy is maintained, but CPU is disrupted and cannot perform other functions
Solution Approach 1:
The DMA controller is enhanced to perform self-service by automatically managing the scatter/gather transfer process. When a DMA transfer completes, the controller autonomously writes the 'End of DMA Transfer' message to the interrupt controller's message register, triggering the interrupt without requiring CPU reprogramming of control registers. This self-service capability maintains transfer reliability while eliminating CPU disruption.
3Ease of operation
If scatter/gather DMA is implemented with chained descriptor lists, then CPU intervention is reduced, but device complexity increases due to additional data structures and automation logic
Solution Approach 1:
The DMA descriptor structure is designed as a universal data structure that can represent any data block in the scatter/gather list. Each descriptor contains fields for source address, destination address, data length, and a pointer to the next descriptor, making it a multi-functional unit that can represent any memory block regardless of its position or size. This universality simplifies the overall system complexity despite the enhanced functionality.
Data Source
AI summary
A method and apparatus for generating a message interrupt. In one embodiment, the method includes writing a predefined data pattern to a predetermined source location in a memory system. One or more first data blocks are also stored in the memory system at one or more first locations, respectively. After storing the one or more first data blocks at the one or more first source locations, creating a first data structure that comprises one or more first source addresses mapped to one or more first destination addresses, respectively, and a predetermined source address mapped to a predetermined destination address, wherein the one or more first source addresses correspond to the one or more first source locations, respectively, and wherein the predetermined source address corresponds to a predetermined source location. The first data structure can be used by a DMA controller to transfer data stored at the one or more first storage locations and to transfer the predetermined data.