Scavenging Metal Layer for High-k Gate Dielectric Oxygen Control
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Solution Overview
Problem
The challenge in scaling down gate dielectric thickness in field effect transistors is exacerbated by high-k gate dielectric materials reacting with oxygen, leading to instability in threshold voltage due to silicon oxide interfacial layer regrowth during high-temperature processing.
Innovation Solution
A metal gate stack comprising a lower metal layer, a scavenging metal layer with specific Gibbs free energy properties, and an upper metal layer is used to capture diffusing oxygen atoms, reducing the equivalent oxide thickness and maintaining constant threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k gate dielectric is used to scale down gate dielectric thickness, then gate leakage current is reduced, but silicon oxide interfacial layer regrowth occurs during high-temperature processing causing threshold voltage instability
Solution Approach 1:
A scavenging metal layer is introduced as an intermediary between the upper metal layer and the high-k gate dielectric. This intermediate layer actively captures oxygen atoms that diffuse toward the dielectric interface, preventing oxygen from reacting with the silicon substrate and forming unwanted silicon oxide. The scavenging metal layer thus mediates the interaction between oxygen and the gate dielectric structure, protecting the interface while allowing the high-k dielectric to function effectively.
Solution Approach 2:
The harmful oxygen atoms that cause silicon oxide regrowth are extracted from the diffusion path by the scavenging metal layer. Instead of allowing oxygen to reach the silicon substrate and form problematic silicon oxide, the oxygen is captured and removed from the critical interface region by the scavenging metal, which has a higher affinity for oxygen. This extraction of oxygen prevents the harmful chemical reaction at the interface.
2Productivity
If gate dielectric thickness is reduced to improve transistor performance, then device scaling is achieved, but leakage current increases exponentially
Solution Approach 1:
The invention changes the dielectric constant parameter of the gate dielectric material from traditional silicon oxide (k≈3.9) to high-k materials (k>7.5). This parameter change allows the physical thickness of the gate dielectric to be reduced while maintaining or improving the electrical insulation properties. The high-k material provides higher capacitance per unit area, enabling better gate control and reduced leakage current despite the reduced thickness.
3Ease of manufacture
If high-temperature anneal in oxygen ambient is applied to process the gate stack, then CMOS integration is achieved, but silicon oxide interfacial layer regrowth occurs
Solution Approach 1:
The scavenging metal layer is positioned beforehand to cushion or protect the silicon-high-k dielectric interface from oxygen exposure during subsequent high-temperature annealing processes. This protective layer acts as a buffer that absorbs the harmful effects of oxygen diffusion and high-temperature processing, preventing the regrowth of silicon oxide at the critical interface even when the structure is exposed to oxygen-containing atmospheres during CMOS integration steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the equivalent oxide thickness of the gate dielectric and stabilizes the threshold voltage of field effect transistors even after high-temperature processing, enhancing their performance and scalability.
Implementation Method 1
the scavenging metal layer captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric
Implementation Method 2
a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy→2x/y M+SiO2 is positive
Data Source
AI summary
A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy→2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.