Switched Capacitor Converter Gate Driver Current Limiting

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Solution Overview

Problem

Switched capacitor converters face challenges in controlling gate voltages of power FETs during startup phases, particularly in high voltage operations, where the supply voltage exceeds the maximum allowed gate voltage, leading to potential damage and inrush currents.

Innovation Solution

The implementation of a dual-mode gate driver circuit system, comprising a first mode for normal operation and a second mode during startup, where the gate driver circuit limits current by disabling switching of one switch and using an amplifier with a reference voltage circuit to control the gate voltage, preventing excessive current flow during capacitor charging.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the supply voltage is increased to achieve high voltage operation, then the voltage conversion capability is improved, but the gate voltage may exceed the maximum allowed gate voltage of FETs causing potential damage

Engineering Contradiction:
Improvevoltage conversion capabilityVSAvoidFET gate voltage safety
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The gate driver circuit is divided into two separate modules: a first gate driver module for normal operation and a second gate driver module for current limiting during startup. This segmentation allows each module to be optimized for its specific function, ensuring safe gate voltage control while maintaining high voltage conversion capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate driver circuit dynamically switches between two operating modes based on the startup signal. During startup, the second module limits current to prevent excessive gate voltage. Once startup is complete, the first module takes over for full-performance operation. This dynamic adaptation resolves the contradiction between power capability and reliability.

Inventive Principle:
Principle #15Dynamics

2Productivity

If fast switching gate driver circuitry is used to achieve required voltage output and efficiency, then the conversion efficiency is improved, but inrush currents may occur during startup phase

Engineering Contradiction:
Improveconversion efficiencyVSAvoidinrush current
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The second gate driver module performs preliminary current limiting during the startup phase before the main switching operation begins. By controlling the charging current of the capacitor in advance, the circuit prevents inrush currents while preparing for efficient normal operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The gate driver operates in periodic phases: initially in current-limited mode during startup, then transitions to full-speed switching mode for efficient operation. This periodic action pattern allows the system to eliminate harmful inrush currents while maintaining high conversion efficiency during the productive phase.

Inventive Principle:
Principle #19Periodic action

3Reliability

If the gate voltage is controlled to stay within maximum limits during startup, then the FET safety is improved, but the switching speed and power transfer capability are reduced

Engineering Contradiction:
ImproveFET gate voltage safetyVSAvoidswitching speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The gate driver circuit dynamically adjusts its operating characteristics based on the startup signal. During startup, voltage limiting is applied to protect FETs. After startup completion, the circuit transitions to full-performance mode with unrestricted switching speed. This dynamic behavior resolves the contradiction between safety and speed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The circuit operates in periodic phases: a startup phase with voltage-limited gate control for safety, followed by a normal operation phase with full-speed switching capability. This temporal separation allows both FET protection and high-speed operation to coexist without compromise.

Inventive Principle:
Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively limits current during the startup phase, preventing inrush currents and ensuring safe operation by maintaining the gate voltage within permissible limits, thereby extending the lifespan of the FETs and improving the efficiency of the converter.

Implementation Method 1

the second gate driver module operates to limit a current provided to the respective power FET

Methodology Applied
Scientific EffectVoltage amplification and comparison:

Implementation Method 2

the reference voltage circuit comprising a current source in series with a first diode-connected n-channel FET connected between the pair of supply voltage rails

Methodology Applied
Scientific EffectDiode effect: Diode

Data Source

PatentUS11736005B2Switched capacitor converter
Publication Date: 2023.08.22 NXP BV
  • US11736005B2 patent drawing
  • US11736005B2 patent drawing
  • US11736005B2 patent drawing

AI summary

The disclosure relates to a switched capacitor converter (SCC) with gate driving circuits for limiting currents provided by switching field effect transistors. Embodiments disclosed include an SCC with gate driver curcuits providing gate voltage signals to power FETs, each gate driver circuit comprising first and second gate driver modules and configured to operate in: a first mode in which the first gate driver module provides a gate voltage signal to a power FET that switches between first and second voltage rails by operation of first and second switches connected between the pair of voltage rails; and a second mode in which, in reponse to enabling of a current limit switching signal, the first gate driver module disables switching of one of the first and second switches and the second gate driver module operates to limit a current provided to the power FET.