Semiconductor Chip SCC Coding for Single-Cell MLC Error Correction
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Solution Overview
Problem
Existing error correction codes in multi-level cell (MLC) memory systems are inefficient in correcting single cell errors and require excessive redundancy bits, leading to increased storage space and power consumption.
Innovation Solution
A novel error correction code (SCC) is developed using a parity check matrix construction that efficiently corrects all single cell errors in MLC memory with the same or fewer redundancy bits, utilizing a generator matrix and parity check matrix generated by setting identity columns and sequential assignment of elements in the Galois field.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing error correction codes (SEC, SEC-DED, SEC-DAEC) are used in MLC memory, then single error correction capability is provided, but they cannot correct all single cell errors occurring in MLC memory and require excessive redundancy bits
Solution Approach 1:
The patent segments the error correction approach by dividing the parity check matrix into specific structural components (identity matrix portion and check bits) that correspond to different error correction functions. This allows specialized handling of single cell errors versus multi-cell errors, improving reliability for the primary use case without requiring excessive redundancy for all possible error patterns.
Solution Approach 2:
The patent applies local quality by designing the parity check matrix with specific structural properties tailored to the characteristics of MLC memory errors. The matrix is constructed with identity matrix columns and specific check bit arrangements that optimize correction capability for single cell errors (which occur most frequently) while using minimal redundancy bits overall.
2Reliability
If more redundancy bits are added to improve error correction capability, then protection against errors is enhanced, but storage space and power consumption increase
Solution Approach 1:
The patent applies partial action by providing error correction capability that is sufficient for the most common error scenarios (single cell errors in MLC memory) without over-engineering for rare error patterns. The parity check matrix is designed to correct all single cell errors and many multi-cell errors using a balanced number of redundancy bits, avoiding the excessive action of attempting to correct all possible error patterns.
3Device complexity
If existing ECC codes are used, then encoding/decoding process is simple, but error correction capability is limited to single errors or adjacent errors
Solution Approach 1:
The patent achieves multi-functionality through the parity check matrix design that can handle multiple error types (single errors, adjacent errors, and single cell errors) within the same correction framework. The matrix structure enables the system to correct single cell errors in MLC memory while maintaining relatively simple encoding and decoding processes, making the solution universally applicable to various error scenarios without requiring complex separate mechanisms.
Data Source
AI summary
The present invention provides a semiconductor chip and system that efficiently corrects single-cell errors in multi-level cell (MLC) memory by utilizing a novel error correction code (SCC) with optimized parity check matrix construction, enabling correction of all single-cell errors while maintaining the same or fewer redundancy bits compared to conventional error correction codes.