Schedule-Based I/O Multiplexing for IC Scan Test

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Solution Overview

Problem

The increasing complexity and power consumption in scan testing of integrated circuits (ICs) due to limited scannable I/O pins, leading to inefficiencies and scalability issues, with existing solutions being costly, complex, or not easily scalable.

Innovation Solution

Implementing schedule-based I/O multiplexing, where available I/Os are assigned to blocks in slots under schedules, allowing for parallel testing of blocks and sharing of I/Os among non-identical blocks, reducing routing resources and congestion, and simplifying reuse in derivative ICs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If scan testing is performed in parallel on all blocks, then test time is reduced, but power consumption increases and I/O pin availability becomes insufficient

Engineering Contradiction:
Improvetest timeVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The IC design is divided into multiple PNR blocks, each with its own scan hub. Scan I/Os are segmented and assigned to specific blocks through schedule-based multiplexing, allowing parallel testing of multiple blocks while controlling power consumption and I/O usage per block.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The scan hub dynamically changes the scan direction (forward or reverse) based on the schedule and block being tested. This dynamic reconfiguration allows the same physical I/O pins to be multiplexed across different blocks at different times, increasing effective I/O availability without adding more pins.

Inventive Principle:
Principle #15Dynamics

2Quantity of substance

If dedicated scan-only pins are added, then scan I/O availability increases, but die area cost and package design complexity increase

Engineering Contradiction:
Improvescan I/O availabilityVSAvoiddie area cost
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The scan hub provides multi-functional capability by allowing the same scan I/O pins to serve multiple different PNR blocks at different times through time-multiplexing and dynamic direction control. This eliminates the need for dedicated scan pins for each block, reducing die area and package complexity while maintaining sufficient scan I/O availability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If scan I/Os are shared among non-identical blocks, then I/O utilization efficiency increases, but scan test complexity increases

Engineering Contradiction:
ImproveI/O utilization efficiencyVSAvoidscan test complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The scan hub acts as an intermediary between the scan I/O pins and the PNR blocks. It manages the complexity of sharing I/Os among non-identical blocks by providing a standardized interface and handling the scheduling, direction control, and multiplexing logic centrally, rather than requiring complex point-to-point control for each block.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Loss of information

If scan direction is modified to maximize pattern compression, then ATE compression efficiency increases, but scan I/O availability is constrained

Engineering Contradiction:
Improvepattern compression efficiencyVSAvoidscan I/O availability
Core Design Contradiction:
Loss of informationVSQuantity of substance

Solution Approach 1:

The scan hub dynamically adjusts the scan direction (forward or reverse) based on the scheduled block and compression requirements. This dynamic reconfiguration allows the system to optimize pattern compression for each block while sequentially serving multiple blocks through the same I/O pins, effectively resolving the conflict between compression efficiency and I/O availability.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11927630B1System and method for schedule-based I/O multiplexing for integrated circuit (IC) scan test
Publication Date: 2024.03.12 MARVELL ASIA PTE LTD
  • US11927630B1 patent drawing
  • US11927630B1 patent drawing
  • US11927630B1 patent drawing

AI summary

An approach is proposed to support schedule-based I/O multiplexing for scan testing of an IC. A plurality of I/Os are assigned to a plurality of blocks in the IC for scan testing based on a set of slots under a set of schedules. Each of the set of slots includes a fixed number of scan input pins/pads and scan output pins/pads of the IC. Each slot is then assigned to a specific block on the IC for the scan test until all of the slots available are utilized. The group of assigned blocks is referred to as a schedule, and all of these blocks belonging to this schedule are scan tested in parallel at the same time. The remaining blocks on the IC are also assigned to the slots until all blocks on the IC are assigned to a schedule to be scan tested.