Scheduled Synchronization Messages With Hardware Packet Pacing

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Solution Overview

Problem

Existing clock synchronization methods, particularly in network devices, suffer from inaccuracies and jitter due to software-based implementations that are non-real-time and sensitive to CPU load, leading to suboptimal synchronization performance and error accumulation.

Innovation Solution

Implementing scheduler circuitry in a network device, such as a hardware accelerator or ASIC, to manage the periodic transmission of time synchronization messages based on a hardware clock, ensuring precise timing and reducing jitter by using packet pacing and time interleaving.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If software-based clock synchronization is used, then implementation flexibility is improved, but timing accuracy and jitter performance deteriorate due to non-real-time execution and CPU load sensitivity

Engineering Contradiction:

Improveimplementation flexibilityVSAvoidtiming accuracy

Core Design Contradiction:

Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent replaces software-based timekeeping and scheduling with a hardware clock and hardware scheduler circuitry. The hardware clock generates precise periodic interrupts, and the hardware scheduler manages message transmission timing in hardware, eliminating the non-deterministic behavior of software-based implementations while maintaining implementation flexibility through configurable parameters.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Adaptability or versatility

If software-based synchronization messages are transmitted, then protocol adaptability is improved, but transmission timing consistency deteriorates due to CPU load and scheduling variability

Engineering Contradiction:

Improveprotocol adaptabilityVSAvoidtransmission timing consistency

Core Design Contradiction:

Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The patent substitutes software message transmission scheduling with hardware-based transmission circuitry that executes transmission at predetermined times determined by hardware clock interrupts. This hardware-based approach ensures consistent transmission timing independent of CPU load, while protocol adaptability is maintained through configurable message formats and intervals.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The system pre-configures transmission schedules and message parameters in advance using the hardware scheduler. The hardware clock and scheduler prepare transmission timing before execution, ensuring that messages are transmitted at precise predetermined intervals without real-time software intervention, thereby maintaining timing consistency.

Inventive Principle:

Principle #10Preliminary action

3Measurement precision

If hardware clock and scheduler circuitry are implemented, then timing precision and jitter reduction are improved, but device complexity increases

Engineering Contradiction:

Improvesynchronization accuracyVSAvoiddevice complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces hardware clock and scheduler circuitry to replace software-based timing mechanisms. While this increases hardware complexity, it dramatically improves synchronization accuracy by eliminating software timing jitter. The hardware components operate independently of CPU load, providing deterministic transmission timing at precise intervals.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20250323743A1Scheduled synchronization messages

Publication Date: 2025.10.16 MELLANOX TECHNOLOGIES LTD(IL)

AI summary

In one embodiments, a system includes a network device including a host interface to receive time synchronization messages generated by software executed by a processing unit of a host device, a hardware clock to maintain a clock time, scheduler circuitry to manage periodic transmission of the time synchronization messages according to the clock time and schedule data provided by the software, and a network interface to transmit the time synchronization messages to at least one clock synchronization follower according to the schedule data and the clock time.