Frequency-Domain Scheduler Acceleration for Parallel 5G Resource Allocation
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Solution Overview
Problem
The computationally intensive tasks performed by the Scheduler in wireless networks, particularly in 5G systems with massive MIMO, are exacerbated by larger bandwidths, more resources to allocate, and shorter time intervals, leading to inefficiencies in frequency-domain scheduling due to sequential dependencies in resource allocation algorithms.
Innovation Solution
Implementing a hardware accelerator or co-processor to offload compute-heavy tasks from CPU cores, enabling parallel execution of frequency-domain scheduling operations, thereby reducing execution time and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-based scheduling is used on CPU cores, then implementation flexibility is maintained, but execution speed and processing efficiency deteriorate due to compute-intensive tasks
Solution Approach 1:
The scheduling system is divided into two parts: a CPU-based control plane that handles high-level scheduling decisions and a hardware accelerator that performs compute-intensive frequency-domain scheduling operations. This segmentation allows the CPU to maintain flexibility while the hardware accelerator provides high-speed execution for specific tasks.
Solution Approach 2:
A hardware accelerator module acts as an intermediary between the CPU and the resource allocation processes. The CPU offloads frequency-domain scheduling tasks to this dedicated hardware component, which is optimized for parallel processing of spectral efficiency calculations and resource allocation decisions.
2Device complexity
If sequential resource allocation algorithms are used in frequency-domain scheduling, then implementation simplicity is maintained, but processing time increases due to sequential dependencies
Solution Approach 1:
The system transitions from sequential single-threaded execution to parallel multi-threaded execution on the hardware accelerator. Multiple resource allocation calculations that were previously performed sequentially are now executed simultaneously across multiple processing units, dramatically reducing processing time while maintaining the same allocation logic.
3Productivity
If hardware accelerators are deployed for parallel processing, then execution speed improves, but device complexity and implementation difficulty increase
Solution Approach 1:
The system is segmented into a control plane running on the CPU and a data plane running on the hardware accelerator. This clear separation allows each component to be optimized independently: the CPU handles complex control logic while the hardware accelerator focuses on high-speed numerical computations for resource allocation.
Solution Approach 2:
The hardware accelerator is designed as a universal platform that can handle multiple types of scheduling algorithms and resource allocation tasks. It provides a configurable architecture that can adapt to different wireless communication standards and scheduling requirements without requiring complete redesign.
4Quantity of substance
If more resources are allocated for massive MIMO in 5G networks, then network capacity increases, but computational load on the scheduler increases significantly
Solution Approach 1:
The patent replaces software-based computational mechanisms with hardware-based parallel processing mechanisms. The hardware accelerator uses dedicated circuitry and parallel computing architectures to perform spectral efficiency calculations and resource allocation for massive MIMO, reducing the computational burden on general-purpose CPU cores.
Data Source
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AI summary
Methods and apparatuses are provided for hardware acceleration for a frequency domain scheduler. An example method includes receiving an instruction from a processor core to process a job for determining an allocation of a set of resources to one or more users, the set of resources corresponding to a transmission layer in a transmission time interval; processing the job by determining which of the one or more users is to be allocated on each of the respective resources in the set based on a first array stored in a memory associated with a metric of each of one or more users for each of the resources in the set, and a second array stored in the memory associated with a buffer size of each of the one or more users; and in response to successfully completing the job, sending an indication of the determined allocation to the processor core.