Scheduler Circuit for Fair Cryptographic Hardware Sharing
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Solution Overview
Problem
Existing cryptographic hardware implementations, such as AES-GCM, face challenges in fairness and efficiency when shared among multiple users or data streams due to sequential operations and state tracking requirements, leading to serialized operations and increased memory footprint.
Innovation Solution
A scheduler circuit splits data transfers into fixed-size partial transfers, allowing sequential execution by a copy engine across multiple contexts, using stored hash keys and block counters to maintain fairness and efficiency without requiring separate authentication tags for each split.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If cryptographic hardware is shared among multiple users with sequential operations, then hardware utilization is improved, but fairness deteriorates due to serialized operations
Solution Approach 1:
The patent divides a data transfer into multiple fixed-size chunks, where each chunk can be independently encrypted. This segmentation allows the cryptographic hardware to process one chunk at a time while maintaining fairness across multiple users, as each user's data is processed in fixed time slices rather than being blocked by large sequential transfers from other users.
2Reliability
If separate authentication tags are used for each block in encrypted data stream, then security is improved, but memory footprint increases
Solution Approach 1:
The patent combines multiple fixed-size encrypted chunks into a single authentication tag. Instead of generating separate authentication tags for each chunk or block, the system processes multiple chunks through the cryptographic hardware and produces one consolidated authentication tag for the entire data transfer, significantly reducing the memory required to store authentication data.
3Loss of time
If transfer size restrictions are imposed to support fairness, then fairness is improved, but productivity deteriorates due to multiple small transfers
Solution Approach 1:
The system automatically segments large data transfers into fixed-size chunks internally, allowing the cryptographic hardware to process them in manageable portions with guaranteed fairness, while the overall transfer maintains high productivity since the segmentation is transparent and efficient.
Solution Approach 2:
The patent implements periodic processing of fixed-size chunks through the cryptographic hardware, creating a rhythmic, predictable pattern of encryption operations that ensures fairness across users while maintaining overall transfer efficiency through continuous periodic processing rather than blocking.
Data Source
AI summary
Apparatuses, systems, and techniques for supporting fairness of multiple context sharing cryptographic hardware. An accelerator circuit includes a copy engine (CE) with AES-GCM hardware configured to perform both encryption and authentication of data transfers for multiple applications or multiple data streams in a single application or belonging to a single user. The CE splits a data transfer of a specified size into a set of partial transfers. The CE sequentially executes the set of partial transfers using a context for a period of time (e.g., a timeslice) for an application. The CE stores in a secure memory for the application one or more data for encryption or decryption (e.g., a hash key, a block counter, etc.) computed from a last partial transfer. The one or more data for encryption or decryption are retrieved and used when data transfers for the application is resumed by the CE.