Scheduler Inter-Group Intra-Group Picking Mechanism

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Solution Overview

Problem

Conventional schedulers face challenges in achieving high frequency due to fragmentation issues when dividing instructions among multiple single-instruction pickers, leading to uneven distribution and underutilization of execution lanes.

Innovation Solution

A scheduler with inter-group and intra-group picking mechanisms that can dispatch multiple instructions per cycle by selecting multiple ready groups and picking instructions based on priority or age, allowing for efficient dispatch of instructions across multiple execution units.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If instructions are divided among multiple single-instruction pickers, then device complexity is reduced, but productivity decreases due to fragmentation and uneven distribution

Engineering Contradiction:
Improvepicker structureVSAvoidinstruction dispatch efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The picker is segmented into multiple pickers (first picker, second picker, etc.), each capable of independently selecting instructions. This segmentation allows parallel operation of multiple pickers to select multiple instructions simultaneously, improving throughput while maintaining manageable complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple pickers are merged into a unified picker structure that shares common resources (instruction silo, execution units). This merging enables coordinated operation where multiple pickers can select instructions from different groups without duplicating entire picker systems, achieving high productivity with controlled complexity

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If multiple ready groups are picked simultaneously, then productivity increases through parallel dispatch, but device complexity increases due to inter-group arbitration requirements

Engineering Contradiction:
Improveinstructions per cycleVSAvoidarbitration mechanism
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Instructions are pre-grouped into age-based groups before the picking process. This preliminary organization by age allows the arbitration mechanism to operate on pre-sorted data, reducing the complexity of real-time arbitration while enabling multiple groups to be selected efficiently based on their age priority

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The arbitration mechanism dynamically adapts to the number of ready groups. When multiple groups are ready, the system activates inter-group arbitration to select appropriate groups; when only one group is ready, the system simplifies to intra-group picking only. This dynamic behavior optimizes productivity while managing complexity based on actual conditions

Inventive Principle:
Principle #15Dynamics

3Reliability

If age-based priority arbitration is implemented, then reliability of instruction ordering is improved, but device complexity increases due to additional arbitration logic

Engineering Contradiction:
Improveinstruction age priorityVSAvoidarbitration logic
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The arbitration logic operates on a simple parameter - instruction age - which is already available from the instruction silo organization. By changing the arbitration criterion to a single parameter (age group) rather than complex dependency analysis, the system achieves reliable age-based priority while minimizing arbitration logic complexity

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The age group information is copied from the instruction silo structure to the picker groups. This copying of age metadata enables the arbitration mechanism to make reliable decisions based on pre-computed age information without duplicating the entire instruction dependency analysis logic, reducing arbitration complexity while maintaining reliability

Inventive Principle:
Principle #26Copying

Data Source

PatentUS10089114B2Multiple instruction issuance with parallel inter-group and intra-group picking
Publication Date: 2018.10.02 QUALCOMM INC
  • US10089114B2 patent drawing
  • US10089114B2 patent drawing
  • US10089114B2 patent drawing

AI summary

A scheduler with a picker block capable of dispatching multiple instructions per cycle is disclosed. The picker block may comprise an inter-group picker and an intra-group picker. The inter-group picker may be configured to pick multiple ready groups when there are two or more ready groups among a plurality of groups of instructions, and pick a single ready group when the single ready group is the only ready group among the plurality of groups. The intra-group picker may be configured to pick one ready instruction from each of the multiple ready groups when the inter-group picker picks the multiple ready groups, and to pick multiple ready instructions from the single ready group when the inter-group picker picks the single ready group.