Scheduler Queue Assignment Logic for Processor Throughput

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Solution Overview

Problem

Processor pipelines face inefficiencies in executing instructions due to imbalances in the number of available operations (ops) and the capacity of execution units, leading to suboptimal utilization and throughput.

Innovation Solution

The implementation of scheduler queue assignment logic that separates ops into streams based on type and determines valid assignment permutations to ensure ops are executed by capable execution units, dynamically assigning ops to maximize throughput by considering occupancy status and selecting valid permutations that avoid overloading certain queues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If ops are assigned to scheduler queues without considering execution unit capabilities, then assignment simplicity is improved, but execution unit utilization deteriorates

Engineering Contradiction:
Improveassignment simplicityVSAvoidexecution unit utilization
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The system pre-establishes capability mappings between execution units and op types, and pre-determines valid assignment permutations. This preliminary preparation allows the scheduler to quickly assign ops without complex runtime analysis, resolving the contradiction between assignment simplicity and execution unit utilization.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The scheduler dynamically selects from pre-computed valid assignment permutations based on current queue occupancy status. This dynamic selection adapts to varying operational conditions while maintaining assignment efficiency, improving execution unit utilization without sacrificing simplicity.

Inventive Principle:
Principle #15Dynamics

2Productivity

If all scheduler queues are assigned ops in every cycle, then throughput is improved, but queue overload deteriorates

Engineering Contradiction:
ImprovethroughputVSAvoidqueue overload
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system computes assignment permutations for all possible op counts (1 to N) in advance. The scheduler then selects the appropriate partial assignment based on current conditions, allowing throughput optimization without causing queue overload by assigning only the appropriate number of ops.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The scheduler monitors queue occupancy status and uses this feedback to select appropriate assignment permutations. This feedback mechanism ensures that ops are assigned in a way that maximizes throughput while preventing any single queue from becoming overloaded.

Inventive Principle:
Principle #23Feedback

3Manufacturing precision

If scheduler computes all possible assignment permutations, then assignment optimality is improved, but computational complexity deteriorates

Engineering Contradiction:
Improveassignment optimalityVSAvoidcomputational complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

All assignment permutations are pre-computed and stored during system initialization. This preliminary computation moves the computational burden from runtime to setup time, achieving assignment optimality without increasing runtime computational complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system creates a static copy of all valid assignment permutations and stores them in a lookup table. During operation, the scheduler simply retrieves the appropriate pre-computed permutation based on current conditions, avoiding complex runtime calculations while maintaining optimality.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS11294678B2Scheduler queue assignment
Publication Date: 2022.04.05 ADVANCED MICRO DEVICES INC
  • US11294678B2 patent drawing
  • US11294678B2 patent drawing
  • US11294678B2 patent drawing

AI summary

Systems, apparatuses, and methods for implementing scheduler queue assignment logic are disclosed. A processor includes at least a decode unit, scheduler queue assignment logic, scheduler queues, pickers, and execution units. The assignment logic receives a plurality of operations from a decode unit in each clock cycle. The assignment logic includes a separate logical unit for each different type of operation which is executable by the different execution units of the processor. For each different type of operation, the assignment logic determines which of the possible assignment permutations are valid for assigning different numbers of operations to scheduler queues in a given clock cycle. The assignment logic receives an indication of how many operations to assign in the given clock cycle, and then the assignment logic selects one of the valid assignment permutations for the number of operations specified by the indication.