Processor Scheduler Queue Programmable Priority Encoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional scheduler queue operations in processors face bottlenecks due to fixed priority encoding, leading to inefficiencies and power consumption issues, particularly in maintaining age order and handling multi-pipeline execution units.
Innovation Solution
Implementing a programmable priority encoding system using an ancestry table to track the relative age order of operations, eliminating the need for shifting and collapsing, and allowing arbitrary priority allocation through a post wake unit and wake array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed priority encoding is used in scheduler queue operations, then implementation is simple, but processing efficiency deteriorates due to bottlenecks in maintaining age order
Solution Approach 1:
The patent implements dynamic priority encoding where the priority of queue entries is not fixed but changes based on their age and readiness status. The system dynamically adjusts which entries are selected for execution by comparing age relationships and readiness states, allowing the scheduler to adapt to varying workloads and maintain optimal processing efficiency without requiring complex structural changes to the queue itself.
2Stability of the object's composition
If shifting and collapsing operations are performed to maintain age order, then age relationships are preserved, but power consumption increases and scheduling speed decreases
Solution Approach 1:
The patent extracts the age relationship information from the physical position of entries in the queue and stores it separately in an ancestry table. This allows the age order to be maintained through data structures rather than physical shifting operations, eliminating the need for continuous shifting and collapsing to preserve age relationships, thereby reducing power consumption and improving scheduling speed.
3Speed
If dedicated pipeline queues are used for multi-pipeline execution units, then processing speed increases, but bottlenecking problems occur and scheduling flexibility is reduced
Solution Approach 1:
The patent implements a universal scheduler queue that can service multiple pipeline types (EX pipelines for arithmetic logic and AG pipelines for address generation) through a single unified structure. The ancestry table and priority encoding mechanism work together to efficiently allocate operations to any available pipeline based on their specific requirements, providing both high processing speed and flexible scheduling capability without the bottlenecking problems of dedicated queues.
4Ease of manufacture
If conventional fixed priority encoding is used, then implementation is straightforward, but operations cannot be efficiently prioritized based on readiness and age
Solution Approach 1:
The patent introduces an ancestry table as an intermediary data structure that stores age relationship information between queue entries. This intermediary allows the system to efficiently determine which operations are older than others without complex comparison logic, enabling prioritization based on both age and readiness status while maintaining relatively simple implementation through the use of this intermediate storage mechanism.
Data Source
AI summary
A method and processor are described for implementing programmable priority encoding to track relative age order of operations in a scheduler queue. The processor may comprise a scheduler queue configured to maintain an ancestry table including a plurality of consecutively numbered row entries and a plurality of consecutively numbered columns. Each row entry includes one bit in each of the columns. Pickers are configured to pick an operation that is ready for execution based on the age of the operation as designated by the ancestry table. The column number of each bit having a select logic value indicates an operation that is older than the operation associated with the number of the row entry that the bit resides in.