Processor Scheduler Source Tag Segmentation
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Solution Overview
Problem
The timing constraints in processor schedulers for out-of-order execution are challenging due to the complexity of broadcasting source tags across all source slots, which can lead to performance penalties and difficulty in increasing processor capabilities.
Innovation Solution
The scheduler divides source slots into fast and slow slots, broadcasting source tags immediately to fast slots and delaying the broadcast to slow slots, allowing for reduced timing constraints and improved clock speeds by processing only a subset of slots in the current cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the scheduler queue size is increased to enhance out-of-order capabilities, then the processor can schedule more instructions, but the timing constraints for broadcasting source tags become more difficult to meet
Solution Approach 1:
The source slots are divided into two distinct subsets: first subset source slots that receive source tags in the current cycle, and second subset source slots that receive source tags in a subsequent cycle. This segmentation allows the scheduler to handle larger queue sizes by breaking down the timing requirements into manageable segments, resolving the contradiction between queue size and timing complexity.
2Reliability
If source tags are broadcast to all source slots in the current cycle, then all instructions can be updated with latest source availability, but the timing constraints become too strict to implement
Solution Approach 1:
The broadcast operation is segmented into two phases: current cycle broadcast to first subset source slots, and subsequent cycle broadcast to second subset source slots. This maintains reliable source tracking while reducing timing constraints to implementable levels.
Solution Approach 2:
Source tags are preliminarily broadcast to the first subset source slots in the current cycle before completing the broadcast to all slots. This preliminary action ensures that critical updates are applied immediately while deferring less time-sensitive updates to the subsequent cycle.
3Measurement precision
If the scheduler processes all source slots in each cycle, then source tracking is complete and accurate, but power consumption increases and clock speed is limited
Solution Approach 1:
The source slot processing is segmented into two groups handled at different times. This allows the scheduler to maintain complete and accurate source tracking while reducing the number of operations performed in each clock cycle, thereby lowering power consumption and enabling higher clock speeds.
Solution Approach 2:
The broadcast operation is performed periodically in two stages: first stage in the current cycle for first subset slots, and second stage in the subsequent cycle for second subset slots. This periodic staged approach reduces instantaneous power requirements while maintaining tracking completeness.
Data Source
AI summary
A processor includes an execution unit to execute instructions and a scheduler unit to store a queue of instructions for execution by the execution unit. The scheduler unit includes a wake array including a plurality of source slots to store source identifiers for sources associated with the instructions, a picker to schedule a particular instruction for execution in the execution unit, broadcast a destination identifier associated with the particular instruction to a first subset of the source slots, and a delay element to receive the destination identifier broadcast by the picker and communicate a delayed version of the destination identifier to a second subset of the source slots different from the first subset.