Hardware Scheduler Traversal for High-Speed Network Traffic Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traffic management in high-speed network ports, such as those found in optical line terminals, is challenging due to the complexity of scheduling, congestion management, and rate limiting, which traditional CPU-based software solutions struggle to handle efficiently.
Innovation Solution
A traffic management system that incorporates an accelerator circuit with a memory to store a data structure, allowing for hardware acceleration of scheduling operations, including a traverse operation to update and store data across multiple iterations, thereby offloading CPU-intensive tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CPU executes software for traffic management, then implementation flexibility is improved, but processing speed deteriorates for high-speed ports
Solution Approach 1:
The patent replaces the CPU-based software execution model with a hardware accelerator that uses dedicated circuitry to perform traffic management functions. The accelerator circuit includes a scheduler, queue manager, and packet processor that operate independently of the CPU, substituting the mechanical/software-based processing with a hardware-based system that achieves significantly higher processing speeds for high-speed ports while maintaining the necessary traffic management capabilities.
Solution Approach 2:
The traffic management system is divided into separate functional modules: a queue manager for packet queuing, a scheduler for scheduling decisions, and a packet processor for actual packet handling. This segmentation allows each component to be optimized independently and enables parallel processing, resolving the contradiction between flexible implementation and high processing speed by distributing the workload across specialized hardware units rather than relying on a single CPU.
2Speed
If hardware accelerator is added, then processing speed is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple traffic management functions into a single integrated accelerator circuit. The queue manager, scheduler, and packet processor are combined in one hardware unit that shares common resources such as memory and control logic. This merging approach achieves high processing speed while minimizing the increase in device complexity by eliminating the need for multiple separate hardware components and reducing inter-component communication overhead.
Solution Approach 2:
The accelerator circuit is designed as a universal traffic management unit that can handle multiple packet types, priority levels, and scheduling algorithms through a single hardware structure. The scheduler can implement different scheduling policies (FIFO, priority queuing, WFQ, DWRR) by configuring the same hardware resources, making the system multi-functional without requiring separate dedicated hardware for each function, thus improving speed with minimal complexity increase.
Data Source
Figure 1
Figure 2~3
Figure 4~7
AI summary
An example traffic management system (14) for a network device includes: a first memory storing queues of packets received by the network device; a second memory (52) storing data of a scheduler (904) for the queues that schedules transmission of the packets to a port (15) of the network device; and an accelerator circuit (50) including a third memory (704) to store a data structure, the accelerator circuit (50) coupled to the second memory (52) and operable to: load, for a first iteration of a traverse operation in response to a command, a field of the data structure in the third memory (704) with data from a first node of the scheduler (904); update, during the first iteration of the traverse operation, the field of the data structure in the third memory (704); and store, during the first iteration of the traverse operation, updated data from the field to the first node in the second memory (52).