Programmable Scheduling Module for SPI Frame Interleaving
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Solution Overview
Problem
Manufacturers of embedded semiconductor devices face challenges in determining a common standard for interleaving Serial Peripheral Interface (SPI) frames within serialized timer channels, leading to increased die size and development time due to the need for multiple hard state machines to support different customer requirements, and software-based implementations significantly impact processing performance.
Innovation Solution
A scheduling module with a programmable register array and multiplexers that selectively couples data sources to a serial communication interface based on source identifier values, enabling flexible and high-speed scheduling of SPI frames and timer channels, reducing the need for multiple hard state machines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple hard state machines are used to support different interleaving rules, then adaptability to different customer requirements is improved, but device complexity and die size increase
Solution Approach 1:
The patent implements a single hard state machine that can be configured to support multiple different interleaving rules through programmable control logic and configuration registers. This universal approach allows one state machine to perform the functions of multiple dedicated state machines, thereby supporting adaptability to different customer requirements while avoiding the increase in device complexity and die size that would result from implementing multiple separate state machines.
2Adaptability or versatility
If software-based scheduling is used, then adaptability to different scheduling rules is improved, but processing performance deteriorates
Solution Approach 1:
The patent replaces software-based scheduling with a hardware-based hard state machine implementation. This substitution transfers the scheduling functionality from the software domain (which offers flexibility but poor performance) to the hardware domain (which provides high-speed operation). The hard state machine executes scheduling decisions directly in hardware, achieving high-speed operation while maintaining adaptability through configurable control logic that can be programmed to support different interleaving rules without requiring software interpretation.
3Ease of manufacture
If a single IC device supports multiple interleaving requirements, then manufacturing efficiency is improved, but device complexity increases
Solution Approach 1:
The patent employs a universal hard state machine design that can be configured to meet multiple different interleaving requirements through programming and configuration rather than through hardware duplication. This approach allows a single IC device to support multiple customer requirements while avoiding the manufacturing complexity and increased die size that would result from incorporating multiple dedicated state machines, thereby improving manufacturing efficiency without significantly increasing device complexity.
Data Source
AI summary
A scheduling module arranged to schedule the transmission of data from a plurality of data sources over a serial communication interface. The scheduling module comprises a register array and is arranged to selectively couple one of the data sources to the serial communication interface based at least partly on a source identifier value stored within a currently selected register within the register array. The scheduling module is further arranged to select a next sequential register within the register array upon receipt of a trigger signal.