Scheduling Support Circuitry for Low-Power Efficiency Clusters
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Hybrid architectures with performance and efficiency cores experience significant performance degradation when transitioning to low power modes, leading to up to 55% reduction in performance due to frequency reduction.
Innovation Solution
Implementing scheduling support circuitry that dynamically allocates tasks between performance and efficiency cores, utilizing a global table to optimize core utilization and maintain performance while conserving power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If frequency of running cores is reduced to achieve low power mode, then power consumption is reduced, but performance is degraded by up to 55%
Solution Approach 1:
The processor is segmented into two distinct core types: performance cores and efficiency cores. Each core type is optimized for different workloads and power characteristics. The scheduler divides tasks between these segments based on power performance characteristics, allowing the system to achieve low power mode without significant performance degradation by utilizing efficiency cores that maintain lower frequencies while consuming less power.
Solution Approach 2:
Different core types are assigned different operational characteristics tailored to their specific functions. Performance cores operate at higher frequencies when needed for performance-critical tasks, while efficiency cores operate at lower frequencies optimized for power consumption. This local differentiation of quality allows the system to optimize the contradiction between power and performance at the core level.
2Use of energy by moving object
If tasks are scheduled on efficiency cores to conserve power, then energy efficiency is improved, but task execution performance may be reduced
Solution Approach 1:
The scheduler dynamically adjusts task placement between performance and efficiency cores based on real-time power performance characteristics. This dynamic scheduling allows the system to adapt to changing workload conditions, selecting the appropriate core type for each task to optimize the balance between energy efficiency and task execution performance.
Solution Approach 2:
The system changes operational parameters such as core frequency and task affinity based on power performance characteristics. By adjusting these parameters dynamically, the scheduler can select efficiency cores with lower frequencies for power-saving scenarios while maintaining acceptable performance, and switch to performance cores when higher performance is required.
3Adaptability or versatility
If hybrid architecture with performance and efficiency cores is implemented, then power management flexibility is improved, but system complexity increases
Solution Approach 1:
Both performance cores and efficiency cores are designed to execute the same instruction set and support the same software ecosystem, providing multi-functionality. This universality allows the scheduler to manage both core types using similar mechanisms, reducing the complexity increase that would otherwise result from having completely separate processing architectures.
Solution Approach 2:
The scheduler acts as an intermediary between the operating system and the heterogeneous core architecture. It translates high-level scheduling decisions into appropriate core selections, abstracting the complexity of the hybrid architecture from the software layer and providing a simplified interface for power management while maintaining flexibility.
Data Source
AI summary
Apparatus and method including scheduling support circuitry for scheduling performance-oriented tasks on an efficiency core cluster. For example, a processor of one embodiment comprises: a first core cluster comprising a first plurality of cores; a second core cluster comprising a second plurality of cores, the second plurality of cores comprising cores which are physically larger and operable at relatively higher performance and power levels than the first plurality of cores; management circuitry to allocate the first core cluster and the second core cluster to task processing zones based on one or more energy/performance bias values, the task processing zones to include a performance zone for processing performance-oriented tasks, wherein when the first core cluster is capable of meeting a maximum achievable performance level determined based on the one or more energy/performance bias values, the management circuitry is to assign the first core cluster to the performance zone.