Scheduling Unit Timing Shift Avoids Bank Conflict

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Solution Overview

Problem

In multi-bank memory systems, bank conflicts occur when multiple load/store units attempt to access the same bank, leading to performance deterioration, and existing solutions fail to effectively prevent these conflicts.

Innovation Solution

An apparatus and method that replace access instructions causing bank conflicts by changing the execute timing of the first instruction to a timing prior to the original, allowing data to be read from the bank at the new timing, thereby preventing simultaneous access to the same bank by different load/store units.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple load/store units access the same bank simultaneously, then data processing parallelism is improved, but bank conflict occurs causing performance deterioration

Engineering Contradiction:
Improvedata processing parallelismVSAvoidperformance stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The scheduling unit performs preliminary analysis of access instructions to predict potential bank conflicts before execution. When a conflict is predicted, the execute timing of the first instruction is changed to a prior timing, allowing the data to be read from the bank at this new timing. This preliminary intervention prevents the bank conflict from occurring in the first place, maintaining both parallelism and performance stability.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If access instructions are modified to prevent bank conflicts, then performance stability is improved, but instruction execution timing complexity increases

Engineering Contradiction:
Improveperformance stabilityVSAvoidinstruction execution timing control
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A scheduling unit is introduced as an intermediary component between the instruction fetch unit and the load/store units. This scheduling unit receives access instructions, predicts potential bank conflicts, and modifies execute timing only when necessary. By placing this intelligence in a dedicated intermediary component rather than distributing complexity throughout the system, the patent achieves performance stability while managing timing control complexity in a localized manner.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If the execute timing of instructions is changed to avoid conflicts, then bank conflict prevention is improved, but data access timing precision requirements increase

Engineering Contradiction:
Improvebank conflict avoidanceVSAvoiddata access timing precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The system changes the execute timing of the first instruction to a prior timing before the original execute timing, allowing the data to be read from the bank at this new timing. By performing this timing adjustment preliminarily and providing the data to the load/store unit at the original execute timing through buffering, the system achieves bank conflict avoidance while managing timing precision requirements through coordinated control.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8214617B2Apparatus and method of avoiding bank conflict in single-port multi-bank memory system
Publication Date: 2012.07.03 SAMSUNG ELECTRONICS CO LTD
  • US8214617B2 patent drawing
  • US8214617B2 patent drawing
  • US8214617B2 patent drawing

AI summary

Provided are a method and apparatus for avoiding bank conflict. A first instruction that is one of access instructions that are predicted to cause the bank conflict is replaced with a second instruction by changing an execute timing of the first instruction to a timing prior to the execute timing of the first instruction so as for the access instructions not to cause the bank conflict. Next, a load/store unit that is scheduled to access the bank according to the first instruction accesses the bank and reads out a data from the bank at an execute timing of the second instruction, and after that, the load/store unit is allowed to be inputted the read data at the execute timing of the first instruction. Accordingly, although the access instructions that are predicted to cause the bank conflict are allocated to the load/store units, the bank conflict can be prevented, so that it is possible to avoid deterioration in performance due the occurrence of the bank conflict.