Schematic-Driven Digital Circuit Layout Generation
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Solution Overview
Problem
Existing digital circuit layout tools are typically layout-driven, limiting the flexibility and efficiency in generating physical layouts, as they focus on conforming to pre-defined physical design constraints rather than utilizing schematic information.
Innovation Solution
A method and apparatus for performing custom, piecewise digital layout generation, where transistors are selected and placed based on a schematic, allowing for automatic placement and optimization within a digital circuit layout tool, which records steps for generating a physical layout plan and stores them in a database for rapid layout of complex integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If layout-driven tools are used to generate physical layouts, then the layouts conform to pre-defined physical design constraints, but the flexibility and efficiency in generating physical layouts are limited
Solution Approach 1:
The patent inverts the traditional layout-driven approach by implementing a schematic-driven layout generation method. Instead of starting with physical design constraints and forcing the circuit to conform, the system starts with the schematic representation and automatically generates the physical layout while satisfying design constraints, thereby improving both flexibility and efficiency
Solution Approach 2:
The system enables the schematic information to serve itself in generating the physical layout. By utilizing the inherent structural and functional information already present in the schematic, the tool automatically derives the physical layout without requiring manual layout intervention, thus enhancing productivity while maintaining constraint conformance
2Adaptability or versatility
If manual transistor placement is performed in layout tools, then placement flexibility is maintained, but layout time increases significantly
Solution Approach 1:
The system performs preliminary action by automatically generating the physical layout from the schematic before any manual placement is needed. The schematic-driven approach pre-computes optimal transistor placements based on the circuit topology and design constraints, eliminating the need for time-consuming manual placement while preserving flexibility through configurable placement options
Solution Approach 2:
The patent replaces the mechanical manual placement process with an automated computational system. Instead of manually positioning each transistor, the system uses algorithmic processing to automatically determine optimal placements, substituting human manual operations with automated mechanisms that are both faster and equally flexible
3Productivity
If schematic-driven layout generation is implemented, then layout time is reduced and efficiency is improved, but the ability to handle complex design constraints may be compromised
Solution Approach 1:
The system introduces an intermediary computational layer that translates schematic information into physical layouts while mediating the satisfaction of design constraints. This intermediary processing layer automatically handles the complexity of constraint satisfaction by incorporating constraint-checking algorithms that work seamlessly with the schematic-driven generation process, maintaining both efficiency and constraint handling capability
Data Source
AI summary
A method and apparatus for performing custom, piecewise digital layout generation is disclosed. The method comprises selecting, in a schematic of a digital circuit displayed in a digital circuit layout tool, a group of transistors and selecting one of a plurality of rows in a physical layout in which the group of transistors is to be placed. After the group of transistors is selected, the digital circuit layout tool may automatically place transistors of the group of transistors in the one of the plurality of rows of the physical layout. The method further comprises repeating selecting of additional groups of transistors, selecting from the plurality of rows, and automatically placing until all transistors of the digital circuit depicted as in the schematic have been placed for use in generating a physical layout plan for the first digital circuit.